riscv: support kernel-mode Vector

[bjoto]

Pull request for series with
subject: riscv: support kernel-mode Vector
version: 4
url: https://patchwork.kernel.org/project/linux-riscv/list/?series=809674

[bjoto]

Upstream branch: eb46a00
series: https://patchwork.kernel.org/project/linux-riscv/list/?series=809674
version: 4

Pull request is NOT updated. Failed to apply https://patchwork.kernel.org/project/linux-riscv/list/?series=809674
error message:

Cmd('git') failed due to: exit code(128)
  cmdline: git am -s --3way
  stdout: 'Applying: riscv: Add support for kernel mode vector
Using index info to reconstruct a base tree...
M	arch/riscv/include/asm/processor.h
M	arch/riscv/include/asm/vector.h
M	arch/riscv/kernel/Makefile
M	arch/riscv/kernel/process.c
Falling back to patching base and 3-way merge...
Auto-merging arch/riscv/kernel/process.c
Auto-merging arch/riscv/kernel/Makefile
Auto-merging arch/riscv/include/asm/vector.h
Auto-merging arch/riscv/include/asm/processor.h
Applying: riscv: vector: make Vector always available for softirq context
Applying: riscv: Add vector extension XOR implementation
Applying: riscv: sched: defer restoring Vector context for user
Applying: riscv: lib: vectorize copy_to_user/copy_from_user
Using index info to reconstruct a base tree...
M	arch/riscv/lib/uaccess.S
Falling back to patching base and 3-way merge...
Auto-merging arch/riscv/lib/uaccess.S
CONFLICT (content): Merge conflict in arch/riscv/lib/uaccess.S
Patch failed at 0005 riscv: lib: vectorize copy_to_user/copy_from_user
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".'
  stderr: 'error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch'

conflict:

diff --cc arch/riscv/lib/uaccess.S
index 3ab438f30d13,b43fd189b534..000000000000
--- a/arch/riscv/lib/uaccess.S
+++ b/arch/riscv/lib/uaccess.S
@@@ -10,7 -12,16 +12,20 @@@
  	_asm_extable	100b, \lbl
  	.endm
  
++<<<<<<< HEAD
 +SYM_FUNC_START(__asm_copy_to_user)
++=======
+ ENTRY(__asm_copy_to_user)
+ ENTRY(__asm_copy_from_user)
+ #ifdef CONFIG_RISCV_ISA_V
+ 	ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_v, CONFIG_RISCV_ISA_V)
+ 	la	t0, riscv_v_usercopy_thres
+ 	REG_L	t0, (t0)
+ 	bltu	a2, t0, fallback_scalar_usercopy
+ 	tail enter_vector_usercopy
+ #endif
+ ENTRY(fallback_scalar_usercopy)
++>>>>>>> riscv: lib: vectorize copy_to_user/copy_from_user
  
  	/* Enable access to user memory */
  	li t6, SR_SUM
@@@ -180,9 -191,10 +195,15 @@@
  	csrc CSR_STATUS, t6
  	sub a0, t5, a0
  	ret
++<<<<<<< HEAD
 +SYM_FUNC_END(__asm_copy_to_user)
++=======
+ ENDPROC(fallback_scalar_usercopy)
+ ENDPROC(__asm_copy_to_user)
+ ENDPROC(__asm_copy_from_user)
++>>>>>>> riscv: lib: vectorize copy_to_user/copy_from_user
  EXPORT_SYMBOL(__asm_copy_to_user)
 +SYM_FUNC_ALIAS(__asm_copy_from_user, __asm_copy_to_user)
  EXPORT_SYMBOL(__asm_copy_from_user)