riscv: Optimize bitops with Zbb extension

[bjoto]

Pull request for series with
subject: riscv: Optimize bitops with Zbb extension
version: 2
url: https://patchwork.kernel.org/project/linux-riscv/list/?series=785828

[bjoto]

Upstream branch: 8eb8fe6
series: https://patchwork.kernel.org/project/linux-riscv/list/?series=785828
version: 2

Pull request is NOT updated. Failed to apply https://patchwork.kernel.org/project/linux-riscv/list/?series=785828
error message:

Cmd('git') failed due to: exit code(128)
  cmdline: git am --3way
  stdout: 'Applying: riscv: Rearrange hwcap.h and cpufeature.h
Using index info to reconstruct a base tree...
M	arch/riscv/include/asm/cpufeature.h
M	arch/riscv/include/asm/hwcap.h
Falling back to patching base and 3-way merge...
Auto-merging arch/riscv/include/asm/hwcap.h
CONFLICT (content): Merge conflict in arch/riscv/include/asm/hwcap.h
Auto-merging arch/riscv/include/asm/cpufeature.h
Patch failed at 0001 riscv: Rearrange hwcap.h and cpufeature.h
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".'
  stderr: 'error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch'

conflict:

diff --cc arch/riscv/include/asm/hwcap.h
index b7b58258f6c7,141b7109c25c..000000000000
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@@ -67,76 -64,4 +64,79 @@@
  #define RISCV_ISA_EXT_SxAIA		RISCV_ISA_EXT_SSAIA
  #endif
  
++<<<<<<< HEAD
 +#ifndef __ASSEMBLY__
 +
 +#include <linux/jump_label.h>
 +
 +unsigned long riscv_get_elf_hwcap(void);
 +
 +struct riscv_isa_ext_data {
 +	const unsigned int id;
 +	const char *name;
 +	const char *property;
 +};
 +
 +extern const struct riscv_isa_ext_data riscv_isa_ext[];
 +extern const size_t riscv_isa_ext_count;
 +extern bool riscv_isa_fallback;
 +
 +unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
 +
 +#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
 +
 +bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
 +#define riscv_isa_extension_available(isa_bitmap, ext)	\
 +	__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
 +
 +static __always_inline bool
 +riscv_has_extension_likely(const unsigned long ext)
 +{
 +	compiletime_assert(ext < RISCV_ISA_EXT_MAX,
 +			   "ext must be < RISCV_ISA_EXT_MAX");
 +
 +	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
 +		asm_volatile_goto(
 +		ALTERNATIVE("j	%l[l_no]", "nop", 0, %[ext], 1)
 +		:
 +		: [ext] "i" (ext)
 +		:
 +		: l_no);
 +	} else {
 +		if (!__riscv_isa_extension_available(NULL, ext))
 +			goto l_no;
 +	}
 +
 +	return true;
 +l_no:
 +	return false;
 +}
 +
 +static __always_inline bool
 +riscv_has_extension_unlikely(const unsigned long ext)
 +{
 +	compiletime_assert(ext < RISCV_ISA_EXT_MAX,
 +			   "ext must be < RISCV_ISA_EXT_MAX");
 +
 +	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
 +		asm_volatile_goto(
 +		ALTERNATIVE("nop", "j	%l[l_yes]", 0, %[ext], 1)
 +		:
 +		: [ext] "i" (ext)
 +		:
 +		: l_yes);
 +	} else {
 +		if (__riscv_isa_extension_available(NULL, ext))
 +			goto l_yes;
 +	}
 +
 +	return false;
 +l_yes:
 +	return true;
 +}
 +
 +#endif
 +
++=======
++>>>>>>> riscv: Rearrange hwcap.h and cpufeature.h
  #endif /* _ASM_RISCV_HWCAP_H */

[bjoto]

At least one diff in series https://patchwork.kernel.org/project/linux-riscv/list/?series=797472 expired. Closing PR.