Refactoring Microchip PCIe driver and add StarFive PCIe #633
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Add PLDA XpressRICH PCIe host common properties dt-binding doc. PolarFire PCIe host using PLDA IP. Move common properties from Microchip PolarFire PCIe host to PLDA files. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: John Clark <inindev@gmail.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
For Microchip Polarfire PCIe host is PLDA XpressRich IP, move to plda directory. Prepare for refactoring the codes. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Move PLDA PCIe host controller IP registers macros to pcie-plda.h, including bridge registers and PLDA IRQ event number. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
For bridge address base is common PLDA field, Add this to struct mc_pcie first. INTx and MSI codes interrupts codes will get the bridge base address from port->bridge_addr. These codes will be changed to common codes. axi_base_addr is Microchip its own data. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Add PLDA PCIe related data structures by rename data structure name from mc_* to plda_*. axi_base_addr is stayed in struct mc_pcie for it's microchip its own data. The event interrupt codes is still using struct mc_pcie because the event interrupt codes can not be re-used. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Move the common data structures definition to head file for these two data structures can be re-used. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Rename two setup functions to plda prefix. Prepare to re-use these two setup function. For two setup functions names are similar, rename mc_pcie_setup_windows() to plda_pcie_setup_iomems(). Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
If other vendor do not select PCI_HOST_COMMON, the driver data is not struct pci_host_bridge. Move calling platform_get_drvdata() to mc_platform_init(). Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Move setup functions to common pcie-plda-host.c. So these two functions can be re-used. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Rename mc_* to plda_* for IRQ functions and related IRQ domain ops data instances. MSI, INTx interrupt code and IRQ init code are all can be re-used. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
The number of events is different across platforms. In order to share interrupt processing code, add a variable that defines the number of events so that it can be set per-platform instead of hardcoding it. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
As PLDA dts binding doc(Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an interrupt controller. Microchip Polarfire PCIe add some PCIe interrupts base on PLDA IP interrupt controller. Microchip Polarfire PCIe additional intrerrupts: EVENT_PCIE_L2_EXIT EVENT_PCIE_HOTRST_EXIT EVENT_PCIE_DLUP_EXIT EVENT_SEC_TX_RAM_SEC_ERR EVENT_SEC_RX_RAM_SEC_ERR .... Both codes of request interrupts and mc_event_handler() contain additional interrupts symbol names, these can not be re-used. So add a new plda_event_handler() functions, which implements PLDA interrupt defalt handler, add request_event_irq() callback function to compat Microchip Polorfire PCIe additional interrupts. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
The INTx and MSI interrupt event num is different in Microchip and StarFive platform. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
As PLDA dts binding doc(Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an interrupt controller. PolarFire implements its own PCIe interrupts, additional to the regular PCIe interrupts, due to lack of an MSI controller, so the interrupt to event number mapping is different to the PLDA regular interrupts, necessitating a custom get_events() implementation. Microchip Polarfire PCIe additional intrerrupts: EVENT_PCIE_L2_EXIT EVENT_PCIE_HOTRST_EXIT EVENT_PCIE_DLUP_EXIT EVENT_SEC_TX_RAM_SEC_ERR EVENT_SEC_RX_RAM_SEC_ERR .... plda_get_events() adds interrupt register to PLDA event num mapping codes. All The PLDA interrupts can be seen in new added graph. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
…chip As PLDA dts binding doc(Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an interrupt controller. Microchip PolarFire PCIE event IRQs includes PLDA interrupts and Polarfire their own interrupts. The interrupt irqchip ops includes ack/mask/unmask interrupt ops, which will write correct registers. Microchip Polarfire PCIe additional interrupts require to write Polarfire SoC self-defined registers. So Microchip PCIe event irqchip ops can not be re-used. To support PLDA its own event IRQ process, implements PLDA irqchip ops and add event irqchip field to struct pcie_plda_rp. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Move IRQ related functions to pcie-plda-host.c for re-use these codes. The re-use code including MSI, INTx, event interrupts and IRQ init functions. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
For PLDA DMA interrupts are not all implemented. The non-implemented interrupts should be masked. So add a bitmap field to mask the non- implemented interrupts. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Add PLDA host plda_pcie_host_init()/plda_pcie_host_deinit() and map bus function. So vendor can use it to init PLDA PCIe host core. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Mason Huo <mason.huo@starfivetech.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Add StarFive JH7110 SoC PCIe controller dt-bindings. JH7110 using PLDA XpressRICH PCIe host controller IP. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum
waiting time between exit from a conventional reset and sending the
first configuration request to the device.
As described in PCI base specification r6.0, section 6.6.1 <Conventional
Reset>, there are two different use cases of the value:
- "With a Downstream Port that does not support Link speeds greater
than 5.0 GT/s, software must wait a minimum of 100 ms following exit
from a Conventional Reset before sending a Configuration Request to
the device immediately below that Port."
- "With a Downstream Port that supports Link speeds greater than
5.0 GT/s, software must wait a minimum of 100 ms after Link training
completes before sending a Configuration Request to the device
immediately below that Port."
Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com>
Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Add StarFive JH7110 SoC PCIe controller platform driver codes, JH7110 with PLDA host PCIe core. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Co-developed-by: Kevin Xie <kevin.xie@starfivetech.com> Reviewed-by: Mason Huo <mason.huo@starfivetech.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
As the Starfive JH7110 hardware can't keep two inbound post write in order all the time, such as MSI messages and NVMe completions. If the NVMe completion update later than the MSI, an NVMe IRQ handle will miss. As a workaround, we will wait a while before going to the generic handle here. Verified with NVMe SSD, USB SSD, R8169 NIC. The performance are stable and even higher after this patch. Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com> Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Add PCIe dts configuraion for JH7110 SoC platform. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
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At least one diff in series https://patchwork.kernel.org/project/linux-riscv/list/?series=827217 irrelevant now. Closing PR. |
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Pull request for series with
subject: Refactoring Microchip PCIe driver and add StarFive PCIe
version: 15
url: https://patchwork.kernel.org/project/linux-riscv/list/?series=827217