riscv: add initial support for Canaan Kendryte K230 #841
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The thead,c908 is a RISC-V CPU core from T-HEAD Semiconductor which used in Canaan Kendryte K230 SoC. Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Since K230 was released, K210 is no longer the only SoC in the Kendryte series, so remove the K210 string from the description. Also, add two boards based on k230 to compatible strings to allow them to be used in the dt. Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Add compatible string for Canaan K230 CLINT. Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Add compatible string for Canaan K230 PLIC. Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Add initial dts for CanMV-K230 and K230-EVB powered by Canaan Kendryte K230 SoC [1]. Some key consideration: - Only place BigCore which is 1.6GHz RV64GCBV The existence of cache coherence between the two cores remains unknown since they have dedicated L2 caches. And the factory SDK uses it for other OS by default. I don't know whether the two CPUs on K230 SoC can be used in one system. So only place BigCore here. Meanwhile, although docs from Canaan said 1.6GHz Core with Vector is CPU1, the CSR.MHARTID of this core is 0. - Support for "zba" "zbb" "zbc" "zbs" are tested by hand The user manual of C908 from T-Head does not document it specifically. It just said it supports B extension V1.0. [2] I have tested it by using this [3] which attempts to execute "add.uw", "andn", "clmulr", "bclr" and they doesn't traps on K230. But on JH7110, "clmulr" and "bclr" will trap. - Support for "zicbom" is tested by hand Have tested with some out-of-tree drivers from [4] that need DMA and they do not come to the dts currently. - Support for "zicboz" is tested by hand Have tested with my own bare mental M-Mode program [5] which tries to use zicboz to clear a 64B aligned block and got output[6] shows it supports zicboz. - Cache parameters are inferred from T-Head docs [2] and Canaan docs [1] L1i: 32KB, VIPT 4-Way set-associative, 64B Cacheline L1d: 32KB, VIPT 4-Way set-associative, 64B Cacheline L2: 256KB, PIPT 16-way set-associative, 64B Cacheline The numbers of cache sets are calculated from these parameters. - MMU only supports Sv39 The T-Head docs [2] say the C908 core can be configured to support Sv48 and Sv39 or only Sv39. On K230, I tried to write "riscv,sv48" on mmu-type in dts and boot the mainline kernel. However, it failed during the kernel probe and fell back to Sv39. I also tested it on M-Mode software, writing Sv48 to satp.mode will not trap but will leave the CSR unchanged. While writing Sv39, it will take effect. It shows that this CPU does not support Sv48. - Svpbmt and T-Head MAEE both supported T-Head C908 does support both Svpbmt and T-Head MAEE for page-based memory attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt is used here for mainline kernel support for K230. If the kernel wants to use Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS before entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0 on T-Head MAEE is NonCachable Memory. Once the kernel switches from bare metal to Sv39, It will lose dirty cache line modifications that haven't been written back to the memory. [1] https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html#chapter-1-introduction [2] https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699268369347/XuanTie-C908-UserManual.pdf [3] https://github.com/cyyself/rvb_test [4] https://github.com/cyyself/linux/tree/k230-mainline [5] cyyself/simple-sw-workbench@32657d8 [6] https://gist.github.com/cyyself/aa98b07b8c77bb1d53b5a4c5e67a37cf Signed-off-by: Yangyu Chen <cyy@cyyself.name> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Since K230 has been supported, allow ARCH_CANAAN to be selected to build dt and drivers for it in defconfig. Signed-off-by: Yangyu Chen <cyy@cyyself.name> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
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At least one diff in series https://patchwork.kernel.org/project/linux-riscv/list/?series=842186 irrelevant now. Closing PR. |
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Pull request for series with
subject: riscv: add initial support for Canaan Kendryte K230
version: 7
url: https://patchwork.kernel.org/project/linux-riscv/list/?series=842063