riscv: Support vendor extensions and xtheadvector

[bjoto]

Pull request for series with
subject: riscv: Support vendor extensions and xtheadvector
version: 5
url: https://patchwork.kernel.org/project/linux-riscv/list/?series=850128

[bjoto]

Upstream branch: 6beb6bc
series: https://patchwork.kernel.org/project/linux-riscv/list/?series=850128
version: 5

Pull request is NOT updated. Failed to apply https://patchwork.kernel.org/project/linux-riscv/list/?series=850128
error message:

Cmd('git') failed due to: exit code(128)
  cmdline: git am -s --3way
  stdout: 'Applying: dt-bindings: riscv: Add xtheadvector ISA extension description
Applying: dt-bindings: riscv: cpus: add a vlen register length property
Applying: riscv: vector: Use vlenb from DT
Applying: riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree
Applying: riscv: Extend cpufeature.c to detect vendor extensions
Applying: riscv: Add vendor extensions to /proc/cpuinfo
Applying: riscv: Introduce vendor variants of extension helpers
Using index info to reconstruct a base tree...
M	arch/riscv/errata/thead/errata.c
Falling back to patching base and 3-way merge...
Auto-merging arch/riscv/errata/thead/errata.c
Applying: riscv: cpufeature: Extract common elements from extension checking
Applying: riscv: Convert xandespmu to use the vendor extension framework
Applying: riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT
Using index info to reconstruct a base tree...
M	arch/riscv/include/asm/csr.h
Falling back to patching base and 3-way merge...
Auto-merging arch/riscv/include/asm/csr.h
CONFLICT (content): Merge conflict in arch/riscv/include/asm/csr.h
Patch failed at 0010 riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".'
  stderr: 'error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch'

conflict:

diff --cc arch/riscv/include/asm/csr.h
index 2468c55933cd,e5a35efd56e0..000000000000
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@@ -215,6 -215,13 +215,16 @@@
  #define SMSTATEEN0_SSTATEEN0_SHIFT	63
  #define SMSTATEEN0_SSTATEEN0		(_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
  
++<<<<<<< HEAD
++=======
+ /* VCSR flags */
+ #define VCSR_VXRM_MASK			3
+ #define VCSR_VXRM_SHIFT			1
+ #define VCSR_VXSAT_MASK			1
+ #define VCSR_VXSAT			0x9
+ #define VCSR_VXRM			0xa
+ 
++>>>>>>> riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT
  /* symbolic CSR names: */
  #define CSR_CYCLE		0xc00
  #define CSR_TIME		0xc01