Support Zve32[xf] and Zve64[xfd] Vector subextensions

[bjoto]

Pull request for series with
subject: Support Zve32[xf] and Zve64[xfd] Vector subextensions
version: 5
url: https://patchwork.kernel.org/project/linux-riscv/list/?series=851960

[bjoto]

Upstream branch: 6beb6bc
series: https://patchwork.kernel.org/project/linux-riscv/list/?series=851960
version: 5

Pull request is NOT updated. Failed to apply https://patchwork.kernel.org/project/linux-riscv/list/?series=851960
error message:

Cmd('git') failed due to: exit code(128)
  cmdline: git am -s --3way
  stdout: 'Applying: riscv: vector: add a comment when calling riscv_setup_vsize()
Applying: riscv: smp: fail booting up smp if inconsistent vlen is detected
Applying: riscv: cpufeature: call match_isa_ext() for single-letter extensions
Applying: dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description
Applying: riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection
Applying: riscv: hwprobe: add zve Vector subextensions into hwprobe interface
Using index info to reconstruct a base tree...
M	Documentation/arch/riscv/hwprobe.rst
M	arch/riscv/include/uapi/asm/hwprobe.h
M	arch/riscv/kernel/sys_hwprobe.c
Falling back to patching base and 3-way merge...
Auto-merging arch/riscv/kernel/sys_hwprobe.c
Auto-merging arch/riscv/include/uapi/asm/hwprobe.h
CONFLICT (content): Merge conflict in arch/riscv/include/uapi/asm/hwprobe.h
Auto-merging Documentation/arch/riscv/hwprobe.rst
CONFLICT (content): Merge conflict in Documentation/arch/riscv/hwprobe.rst
Patch failed at 0006 riscv: hwprobe: add zve Vector subextensions into hwprobe interface
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".'
  stderr: 'error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch'

conflict:

diff --cc Documentation/arch/riscv/hwprobe.rst
index b2bcc9eed9aa,fc015b452ebf..000000000000
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@@ -188,6 -188,25 +188,28 @@@ The following keys are defined
         manual starting from commit 95cf1f9 ("Add changes requested by Ved
         during signoff")
  
++<<<<<<< HEAD
++=======
+   * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is
+        supported as defined in the RISC-V ISA manual starting from commit
+        d8ab5c78c207 ("Zihintpause is ratified").
+ 
+   * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
+     supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+ 
+   * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is
+     supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+ 
+   * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is
+     supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+ 
+   * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is
+     supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+ 
+   * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is
+     supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+ 
++>>>>>>> riscv: hwprobe: add zve Vector subextensions into hwprobe interface
  * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
    information about the selected set of processors.
  
diff --cc arch/riscv/include/uapi/asm/hwprobe.h
index 2902f68dc913,6593aedb9d2b..000000000000
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@@ -59,6 -59,12 +59,15 @@@ struct riscv_hwprobe 
  #define		RISCV_HWPROBE_EXT_ZTSO		(1ULL << 33)
  #define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)
  #define		RISCV_HWPROBE_EXT_ZICOND	(1ULL << 35)
++<<<<<<< HEAD
++=======
+ #define		RISCV_HWPROBE_EXT_ZIHINTPAUSE	(1ULL << 36)
+ #define		RISCV_HWPROBE_EXT_ZVE32X	(1ULL << 37)
+ #define		RISCV_HWPROBE_EXT_ZVE32F	(1ULL << 38)
+ #define		RISCV_HWPROBE_EXT_ZVE64X	(1ULL << 39)
+ #define		RISCV_HWPROBE_EXT_ZVE64F	(1ULL << 40)
+ #define		RISCV_HWPROBE_EXT_ZVE64D	(1ULL << 41)
++>>>>>>> riscv: hwprobe: add zve Vector subextensions into hwprobe interface
  #define RISCV_HWPROBE_KEY_CPUPERF_0	5
  #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
  #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)