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ZTE VOU Display Controller | ||
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This is a display controller found on ZTE ZX296718 SoC. It includes multiple | ||
Graphic Layer (GL) and Video Layer (VL), two Mixers/Channels, and a few blocks | ||
handling scaling, color space conversion etc. VOU also integrates the support | ||
for typical output devices, like HDMI, TV Encoder, VGA, and RGB LCD. | ||
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* Master VOU node | ||
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It must be the parent node of all the sub-device nodes. | ||
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Required properties: | ||
- compatible: should be "zte,zx296718-vou" | ||
- #address-cells: should be <1> | ||
- #size-cells: should be <1> | ||
- ranges: list of address translations between VOU and sub-devices | ||
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* VOU DPC device | ||
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Required properties: | ||
- compatible: should be "zte,zx296718-dpc" | ||
- reg: Physical base address and length of DPC register regions, one for each | ||
entry in 'reg-names' | ||
- reg-names: The names of register regions. The following regions are required: | ||
"osd" | ||
"timing_ctrl" | ||
"dtrc" | ||
"vou_ctrl" | ||
"otfppu" | ||
- interrupts: VOU DPC interrupt number to CPU | ||
- clocks: A list of phandle + clock-specifier pairs, one for each entry | ||
in 'clock-names' | ||
- clock-names: A list of clock names. The following clocks are required: | ||
"aclk" | ||
"ppu_wclk" | ||
"main_wclk" | ||
"aux_wclk" | ||
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* HDMI output device | ||
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Required properties: | ||
- compatible: should be "zte,zx296718-hdmi" | ||
- reg: Physical base address and length of the HDMI device IO region | ||
- interrupts : HDMI interrupt number to CPU | ||
- clocks: A list of phandle + clock-specifier pairs, one for each entry | ||
in 'clock-names' | ||
- clock-names: A list of clock names. The following clocks are required: | ||
"osc_cec" | ||
"osc_clk" | ||
"xclk" | ||
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Example: | ||
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vou: vou@1440000 { | ||
compatible = "zte,zx296718-vou"; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
ranges = <0 0x1440000 0x10000>; | ||
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dpc: dpc@0 { | ||
compatible = "zte,zx296718-dpc"; | ||
reg = <0x0000 0x1000>, <0x1000 0x1000>, | ||
<0x5000 0x1000>, <0x6000 0x1000>, | ||
<0xa000 0x1000>; | ||
reg-names = "osd", "timing_ctrl", | ||
"dtrc", "vou_ctrl", | ||
"otfppu"; | ||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>, | ||
<&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>; | ||
clock-names = "aclk", "ppu_wclk", | ||
"main_wclk", "aux_wclk"; | ||
}; | ||
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hdmi: hdmi@c000 { | ||
compatible = "zte,zx296718-hdmi"; | ||
reg = <0xc000 0x4000>; | ||
interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; | ||
clocks = <&topcrm HDMI_OSC_CEC>, | ||
<&topcrm HDMI_OSC_CLK>, | ||
<&topcrm HDMI_XCLK>; | ||
clock-names = "osc_cec", "osc_clk", "xclk"; | ||
}; | ||
}; |
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Documentation/devicetree/bindings/video/bridge/sil-sii8620.txt
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Silicon Image SiI8620 HDMI/MHL bridge bindings | ||
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Required properties: | ||
- compatible: "sil,sii8620" | ||
- reg: i2c address of the bridge | ||
- cvcc10-supply: Digital Core Supply Voltage (1.0V) | ||
- iovcc18-supply: I/O Supply Voltage (1.8V) | ||
- interrupts, interrupt-parent: interrupt specifier of INT pin | ||
- reset-gpios: gpio specifier of RESET pin | ||
- clocks, clock-names: specification and name of "xtal" clock | ||
- video interfaces: Device node can contain video interface port | ||
node for HDMI encoder according to [1]. | ||
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[1]: Documentation/devicetree/bindings/media/video-interfaces.txt | ||
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Example: | ||
sii8620@39 { | ||
reg = <0x39>; | ||
compatible = "sil,sii8620"; | ||
cvcc10-supply = <&ldo36_reg>; | ||
iovcc18-supply = <&ldo34_reg>; | ||
interrupt-parent = <&gpf0>; | ||
interrupts = <2 0>; | ||
reset-gpio = <&gpv7 0 0>; | ||
clocks = <&pmu_system_controller 0>; | ||
clock-names = "xtal"; | ||
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port { | ||
mhl_to_hdmi: endpoint { | ||
remote-endpoint = <&hdmi_to_mhl>; | ||
}; | ||
}; | ||
}; |
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