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Merge branches 'sunxi/defconfig-for-4.8', 'sunxi/drm-fixes-for-4.7' a…
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…nd 'sunxi/dt-for-4.8' into sunxi/for-next
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@mripard
mripard committed May 30, 2016
3 parents 684d2d7 + 13fef09 + 2e7a389 commit 30ce0df
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Showing 12 changed files with 435 additions and 173 deletions.
1 change: 1 addition & 0 deletions arch/arm/boot/dts/axp209.dtsi
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Expand Up @@ -87,6 +87,7 @@

reg_ldo5: ldo5 {
regulator-name = "ldo5";
status = "disabled";
};
};

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91 changes: 84 additions & 7 deletions arch/arm/boot/dts/sun4i-a10.dtsi
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Expand Up @@ -65,17 +65,18 @@
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
<&ahb_gates 44>, <&dram_gates 26>;
clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>,
<&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>;
status = "disabled";
};

framebuffer@1 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
clocks = <&ahb_gates 36>, <&ahb_gates 43>,
<&ahb_gates 44>, <&ahb_gates 46>,
<&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>,
<&dram_gates 25>, <&dram_gates 26>;
status = "disabled";
};
Expand All @@ -84,18 +85,19 @@
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
<&ahb_gates 46>, <&dram_gates 25>,
<&dram_gates 26>;
clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>,
<&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>,
<&dram_gates 25>, <&dram_gates 26>;
status = "disabled";
};

framebuffer@3 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
clocks = <&ahb_gates 34>, <&ahb_gates 36>,
<&ahb_gates 44>, <&ahb_gates 46>,
<&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>,
<&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>;
status = "disabled";
};
Expand Down Expand Up @@ -574,6 +576,81 @@
"dram_de_mp", "dram_ace";
};

de_be0_clk: clk@01c20104 {
#clock-cells = <0>;
#reset-cells = <0>;
compatible = "allwinner,sun4i-a10-display-clk";
reg = <0x01c20104 0x4>;
clocks = <&pll3>, <&pll7>, <&pll5 1>;
clock-output-names = "de-be0";
};

de_be1_clk: clk@01c20108 {
#clock-cells = <0>;
#reset-cells = <0>;
compatible = "allwinner,sun4i-a10-display-clk";
reg = <0x01c20108 0x4>;
clocks = <&pll3>, <&pll7>, <&pll5 1>;
clock-output-names = "de-be1";
};

de_fe0_clk: clk@01c2010c {
#clock-cells = <0>;
#reset-cells = <0>;
compatible = "allwinner,sun4i-a10-display-clk";
reg = <0x01c2010c 0x4>;
clocks = <&pll3>, <&pll7>, <&pll5 1>;
clock-output-names = "de-fe0";
};

de_fe1_clk: clk@01c20110 {
#clock-cells = <0>;
#reset-cells = <0>;
compatible = "allwinner,sun4i-a10-display-clk";
reg = <0x01c20110 0x4>;
clocks = <&pll3>, <&pll7>, <&pll5 1>;
clock-output-names = "de-fe1";
};


tcon0_ch0_clk: clk@01c20118 {
#clock-cells = <0>;
#reset-cells = <1>;
compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
reg = <0x01c20118 0x4>;
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
clock-output-names = "tcon0-ch0-sclk";

};

tcon1_ch0_clk: clk@01c2011c {
#clock-cells = <0>;
#reset-cells = <1>;
compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
reg = <0x01c2011c 0x4>;
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
clock-output-names = "tcon1-ch0-sclk";

};

tcon0_ch1_clk: clk@01c2012c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
reg = <0x01c2012c 0x4>;
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
clock-output-names = "tcon0-ch1-sclk";

};

tcon1_ch1_clk: clk@01c20130 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
reg = <0x01c20130 0x4>;
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
clock-output-names = "tcon1-ch1-sclk";

};

ve_clk: clk@01c2013c {
#clock-cells = <0>;
#reset-cells = <0>;
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122 changes: 122 additions & 0 deletions arch/arm/boot/dts/sun5i-a13.dtsi
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Expand Up @@ -207,14 +207,126 @@
};
};

display-engine {
compatible = "allwinner,sun5i-a13-display-engine";
allwinner,pipelines = <&fe0>;
};

soc@01c00000 {
tcon0: lcd-controller@01c0c000 {
compatible = "allwinner,sun5i-a13-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <44>;
resets = <&tcon_ch0_clk 1>;
reset-names = "lcd";
clocks = <&ahb_gates 36>,
<&tcon_ch0_clk>,
<&tcon_ch1_clk>;
clock-names = "ahb",
"tcon-ch0",
"tcon-ch1";
clock-output-names = "tcon-pixel-clock";
status = "disabled";

ports {
#address-cells = <1>;
#size-cells = <0>;

tcon0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;

tcon0_in_be0: endpoint@0 {
reg = <0>;
remote-endpoint = <&be0_out_tcon0>;
};
};

tcon0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};

pwm: pwm@01c20e00 {
compatible = "allwinner,sun5i-a13-pwm";
reg = <0x01c20e00 0xc>;
clocks = <&osc24M>;
#pwm-cells = <3>;
status = "disabled";
};

fe0: display-frontend@01e00000 {
compatible = "allwinner,sun5i-a13-display-frontend";
reg = <0x01e00000 0x20000>;
interrupts = <47>;
clocks = <&ahb_gates 46>, <&de_fe_clk>,
<&dram_gates 25>;
clock-names = "ahb", "mod",
"ram";
resets = <&de_fe_clk>;
status = "disabled";

ports {
#address-cells = <1>;
#size-cells = <0>;

fe0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;

fe0_out_be0: endpoint@0 {
reg = <0>;
remote-endpoint = <&be0_in_fe0>;
};
};
};
};

be0: display-backend@01e60000 {
compatible = "allwinner,sun5i-a13-display-backend";
reg = <0x01e60000 0x10000>;
clocks = <&ahb_gates 44>, <&de_be_clk>,
<&dram_gates 26>;
clock-names = "ahb", "mod",
"ram";
resets = <&de_be_clk>;
status = "disabled";

assigned-clocks = <&de_be_clk>;
assigned-clock-rates = <300000000>;

ports {
#address-cells = <1>;
#size-cells = <0>;

be0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;

be0_in_fe0: endpoint@0 {
reg = <0>;
remote-endpoint = <&fe0_out_be0>;
};
};

be0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;

be0_out_tcon0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon0_in_be0>;
};
};
};
};
};
};

Expand All @@ -237,6 +349,16 @@
&pio {
compatible = "allwinner,sun5i-a13-pinctrl";

lcd_rgb666_pins: lcd_rgb666@0 {
allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
"PD24", "PD25", "PD26", "PD27";
allwinner,function = "lcd0";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};

uart1_pins_a: uart1@0 {
allwinner,pins = "PE10", "PE11";
allwinner,function = "uart1";
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55 changes: 55 additions & 0 deletions arch/arm/boot/dts/sun5i-q8-common.dtsi
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Expand Up @@ -59,6 +59,36 @@
chosen {
stdout-path = "serial0:115200n8";
};

panel: panel {
compatible = "urt,umsh-8596md-t", "simple-panel";
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <0>;
/* TODO: lcd panel uses axp gpio0 as enable pin */
backlight = <&backlight>;
#address-cells = <1>;
#size-cells = <0>;

panel_input: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon0_out_lcd>;
};
};
};
};

&be0 {
status = "okay";
};

&codec {
pinctrl-names = "default";
pinctrl-0 = <&codec_pa_pin>;
allwinner,pa-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */
status = "okay";
};

&cpu0 {
Expand Down Expand Up @@ -100,6 +130,13 @@
};

&pio {
codec_pa_pin: codec_pa_pin@0 {
allwinner,pins = "PG10";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};

mmc0_cd_pin_q8: mmc0_cd_pin@0 {
allwinner,pins = "PG0";
allwinner,function = "gpio_in";
Expand Down Expand Up @@ -159,6 +196,19 @@
status = "okay";
};

&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_rgb666_pins>;
status = "okay";
};

&tcon0_out {
tcon0_out_lcd: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};

&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_b>;
Expand All @@ -170,11 +220,16 @@
status = "okay";
};

&usb_power_supply {
status = "okay";
};

&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <&reg_usb0_vbus>;
status = "okay";
};
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