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* Samsung S3FWRN5 NCI NFC Controller | ||
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Required properties: | ||
- compatible: Should be "samsung,s3fwrn5-i2c". | ||
- reg: address on the bus | ||
- interrupt-parent: phandle for the interrupt gpio controller | ||
- interrupts: GPIO interrupt to which the chip is connected | ||
- s3fwrn5,en-gpios: Output GPIO pin used for enabling/disabling the chip | ||
- s3fwrn5,fw-gpios: Output GPIO pin used to enter firmware mode and | ||
sleep/wakeup control | ||
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Example: | ||
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&hsi2c_4 { | ||
status = "okay"; | ||
s3fwrn5@27 { | ||
compatible = "samsung,s3fwrn5-i2c"; | ||
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reg = <0x27>; | ||
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interrupt-parent = <&gpa1>; | ||
interrupts = <3 0 0>; | ||
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s3fwrn5,en-gpios = <&gpf1 4 0>; | ||
s3fwrn5,fw-gpios = <&gpj0 2 0>; | ||
}; | ||
}; |
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* STMicroelectronics SAS. ST NCI NFC Controller | ||
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Required properties: | ||
- compatible: Should be "st,st21nfcb-spi" | ||
- spi-max-frequency: Maximum SPI frequency (<= 10000000). | ||
- interrupt-parent: phandle for the interrupt gpio controller | ||
- interrupts: GPIO interrupt to which the chip is connected | ||
- reset-gpios: Output GPIO pin used to reset the ST21NFCB | ||
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Optional SoC Specific Properties: | ||
- pinctrl-names: Contains only one value - "default". | ||
- pintctrl-0: Specifies the pin control groups used for this controller. | ||
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Example (for ARM-based BeagleBoard xM with ST21NFCB on SPI4): | ||
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&mcspi4 { | ||
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status = "okay"; | ||
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st21nfcb: st21nfcb@0 { | ||
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compatible = "st,st21nfcb-spi"; | ||
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clock-frequency = <4000000>; | ||
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interrupt-parent = <&gpio5>; | ||
interrupts = <2 IRQ_TYPE_EDGE_RISING>; | ||
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reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; | ||
}; | ||
}; |
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75
Documentation/devicetree/bindings/net/snps,dwc-qos-ethernet.txt
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* Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC) | ||
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Required properties: | ||
- compatible: Should be "snps,dwc-qos-ethernet-4.10" | ||
- reg: Address and length of the register set for the device | ||
- clocks: Phandles to the reference clock and the bus clock | ||
- clock-names: Should be "phy_ref_clk" for the reference clock and "apb_pclk" | ||
for the bus clock. | ||
- interrupt-parent: Should be the phandle for the interrupt controller | ||
that services interrupts for this device | ||
- interrupts: Should contain the core's combined interrupt signal | ||
- phy-mode: See ethernet.txt file in the same directory | ||
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Optional properties: | ||
- dma-coherent: Present if dma operations are coherent | ||
- mac-address: See ethernet.txt in the same directory | ||
- local-mac-address: See ethernet.txt in the same directory | ||
- snps,en-lpi: If present it enables use of the AXI low-power interface | ||
- snps,write-requests: Number of write requests that the AXI port can issue. | ||
It depends on the SoC configuration. | ||
- snps,read-requests: Number of read requests that the AXI port can issue. | ||
It depends on the SoC configuration. | ||
- snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB | ||
representing 4, then 8 etc. | ||
- snps,txpbl: DMA Programmable burst length for the TX DMA | ||
- snps,rxpbl: DMA Programmable burst length for the RX DMA | ||
- snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during | ||
TX low-power mode. | ||
- phy-handle: See ethernet.txt file in the same directory | ||
- mdio device tree subnode: When the GMAC has a phy connected to its local | ||
mdio, there must be device tree subnode with the following | ||
required properties: | ||
- compatible: Must be "snps,dwc-qos-ethernet-mdio". | ||
- #address-cells: Must be <1>. | ||
- #size-cells: Must be <0>. | ||
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For each phy on the mdio bus, there must be a node with the following | ||
fields: | ||
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- reg: phy id used to communicate to phy. | ||
- device_type: Must be "ethernet-phy". | ||
- fixed-mode device tree subnode: see fixed-link.txt in the same directory | ||
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Examples: | ||
ethernet2@40010000 { | ||
clock-names = "phy_ref_clk", "apb_pclk"; | ||
clocks = <&clkc 17>, <&clkc 15>; | ||
compatible = "snps,dwc-qos-ethernet-4.10"; | ||
interrupt-parent = <&intc>; | ||
interrupts = <0x0 0x1e 0x4>; | ||
reg = <0x40010000 0x4000>; | ||
phy-handle = <&phy2>; | ||
phy-mode = "gmii"; | ||
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snps,en-tx-lpi-clockgating; | ||
snps,en-lpi; | ||
snps,write-requests = <2>; | ||
snps,read-requests = <16>; | ||
snps,burst-map = <0x7>; | ||
snps,txpbl = <8>; | ||
snps,rxpbl = <2>; | ||
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dma-coherent; | ||
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mdio { | ||
#address-cells = <0x1>; | ||
#size-cells = <0x0>; | ||
phy2: phy@1 { | ||
compatible = "ethernet-phy-ieee802.3-c22"; | ||
device_type = "ethernet-phy"; | ||
reg = <0x1>; | ||
}; | ||
}; | ||
}; |
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Netdev private dataroom for 6lowpan interfaces: | ||
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All 6lowpan able net devices, means all interfaces with ARPHRD_6LOWPAN, | ||
must have "struct lowpan_priv" placed at beginning of netdev_priv. | ||
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The priv_size of each interface should be calculate by: | ||
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dev->priv_size = LOWPAN_PRIV_SIZE(LL_6LOWPAN_PRIV_DATA); | ||
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Where LL_PRIV_6LOWPAN_DATA is sizeof linklayer 6lowpan private data struct. | ||
To access the LL_PRIV_6LOWPAN_DATA structure you can cast: | ||
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lowpan_priv(dev)-priv; | ||
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to your LL_6LOWPAN_PRIV_DATA structure. | ||
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Before registering the lowpan netdev interface you must run: | ||
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lowpan_netdev_setup(dev, LOWPAN_LLTYPE_FOOBAR); | ||
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wheres LOWPAN_LLTYPE_FOOBAR is a define for your 6LoWPAN linklayer type of | ||
enum lowpan_lltypes. | ||
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Example to evaluate the private usually you can do: | ||
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static inline sturct lowpan_priv_foobar * | ||
lowpan_foobar_priv(struct net_device *dev) | ||
{ | ||
return (sturct lowpan_priv_foobar *)lowpan_priv(dev)->priv; | ||
} | ||
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switch (dev->type) { | ||
case ARPHRD_6LOWPAN: | ||
lowpan_priv = lowpan_priv(dev); | ||
/* do great stuff which is ARPHRD_6LOWPAN related */ | ||
switch (lowpan_priv->lltype) { | ||
case LOWPAN_LLTYPE_FOOBAR: | ||
/* do 802.15.4 6LoWPAN handling here */ | ||
lowpan_foobar_priv(dev)->bar = foo; | ||
break; | ||
... | ||
} | ||
break; | ||
... | ||
} | ||
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In case of generic 6lowpan branch ("net/6lowpan") you can remove the check | ||
on ARPHRD_6LOWPAN, because you can be sure that these function are called | ||
by ARPHRD_6LOWPAN interfaces. |
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