The include/linux/clk.h header defines dummy implementations for the
various clk_*() functions if HAVE_CLK is not selected to improve build
coverage in randconfig builds.

The dummy implementation of clk_get_rate() returns 0, which causes the
Atmel HLCDC PWM driver's atmel_hlcdc_pwm_config() implementation to end
up calling:

	do_div(clk_period_ns, 0)

On x86, do_div(n, base) will end up evaluating to this:

	n >>= ilog2(base)

with base = 0, the implementation of ilog2() will call ____ilog2_NaN(),
which is purposely undefined and results in a linker failure:

	ERROR: "____ilog2_NaN" [drivers/pwm/pwm-atmel-hlcdc.ko] undefined!

The implementation of do_div() checks that base is a power of 2 before
calling ilog2(). The compiler doesn't optimize this away, presumably
because is_power_of_2() is an inline function and the compiler doesn't
or can't inspect it closely enough. ilog2() being a macro it still ends
up generating the ____ilog2_NaN() because of the constant 0.

The root of the problem is that the driver really should be checking
before possibly dividing by zero. That should eventually be fixed, but
for now just assume that the clock runs at a sensible frequency when
available.

Reported-by: Jim Davis <jim.epost@gmail.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

The slow and system clock should never return a rate of zero, but this
might happen if the clocks property defined in the DT is referencing the
wrong clocks.

Prevent any division by zero from happening by testing the clk_freq
value before calling do_div().

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

This adds a generic PWM framework driver for the PWM controller
found on Allwinner SoCs.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

This is the documentation for the Allwinner SoCs PWM bindings.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

…defconfig-for-3.20' into sunxi/for-next

Conflicts:
	arch/arm/boot/dts/sun7i-a20.dtsi

Merge thermal zone driver from input git tree

Merge the A31s pinctrl driver from pinctrl tree

Merge A10/A20 PWM driver

Linux 3.19-rc6