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Merge pull request #1 from StollD/feature/i915-legacy-5.2.15
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Update i915_legacy to 5.2.15
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@qzed
qzed committed Sep 18, 2019
2 parents 44c79ab + 54590f6 commit ce721a4
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Showing 3 changed files with 128 additions and 26 deletions.
7 changes: 7 additions & 0 deletions drivers/gpu/drm/i915_legacy/i915_reg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2510,6 +2510,13 @@ enum i915_power_well_id {
#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */

#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
#define RING_FORCE_TO_NONPRIV_RW (0 << 28) /* CFL+ & Gen11+ */
#define RING_FORCE_TO_NONPRIV_RD (1 << 28)
#define RING_FORCE_TO_NONPRIV_WR (2 << 28)
#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
#define RING_MAX_NONPRIV_SLOTS 12

#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
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11 changes: 11 additions & 0 deletions drivers/gpu/drm/i915_legacy/intel_cdclk.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2269,6 +2269,17 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
min_cdclk = max(2 * 96000, min_cdclk);

/*
* "For DP audio configuration, cdclk frequency shall be set to
* meet the following requirements:
* DP Link Frequency(MHz) | Cdclk frequency(MHz)
* 270 | 320 or higher
* 162 | 200 or higher"
*/
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
min_cdclk = max(crtc_state->port_clock, min_cdclk);

/*
* On Valleyview some DSI panels lose (v|h)sync when the clock is lower
* than 320000KHz.
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136 changes: 110 additions & 26 deletions drivers/gpu/drm/i915_legacy/intel_workarounds.c
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Original file line number Diff line number Diff line change
Expand Up @@ -981,7 +981,7 @@ bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
}

static void
whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
{
struct i915_wa wa = {
.reg = reg
Expand All @@ -990,9 +990,16 @@ whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
return;

wa.reg.reg |= flags;
_wa_add(wal, &wa);
}

static void
whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
{
whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_RW);
}

static void gen9_whitelist_build(struct i915_wa_list *w)
{
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
Expand All @@ -1005,81 +1012,154 @@ static void gen9_whitelist_build(struct i915_wa_list *w)
whitelist_reg(w, GEN8_HDC_CHICKEN1);
}

static void skl_whitelist_build(struct i915_wa_list *w)
static void skl_whitelist_build(struct intel_engine_cs *engine)
{
struct i915_wa_list *w = &engine->whitelist;

if (engine->class != RENDER_CLASS)
return;

gen9_whitelist_build(w);

/* WaDisableLSQCROPERFforOCL:skl */
whitelist_reg(w, GEN8_L3SQCREG4);
}

static void bxt_whitelist_build(struct i915_wa_list *w)
static void bxt_whitelist_build(struct intel_engine_cs *engine)
{
gen9_whitelist_build(w);
if (engine->class != RENDER_CLASS)
return;

gen9_whitelist_build(&engine->whitelist);
}

static void kbl_whitelist_build(struct i915_wa_list *w)
static void kbl_whitelist_build(struct intel_engine_cs *engine)
{
struct i915_wa_list *w = &engine->whitelist;

if (engine->class != RENDER_CLASS)
return;

gen9_whitelist_build(w);

/* WaDisableLSQCROPERFforOCL:kbl */
whitelist_reg(w, GEN8_L3SQCREG4);
}

static void glk_whitelist_build(struct i915_wa_list *w)
static void glk_whitelist_build(struct intel_engine_cs *engine)
{
struct i915_wa_list *w = &engine->whitelist;

if (engine->class != RENDER_CLASS)
return;

gen9_whitelist_build(w);

/* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
}

static void cfl_whitelist_build(struct i915_wa_list *w)
static void cfl_whitelist_build(struct intel_engine_cs *engine)
{
struct i915_wa_list *w = &engine->whitelist;

if (engine->class != RENDER_CLASS)
return;

gen9_whitelist_build(w);

/*
* WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
*
* This covers 4 register which are next to one another :
* - PS_INVOCATION_COUNT
* - PS_INVOCATION_COUNT_UDW
* - PS_DEPTH_COUNT
* - PS_DEPTH_COUNT_UDW
*/
whitelist_reg_ext(w, PS_INVOCATION_COUNT,
RING_FORCE_TO_NONPRIV_RD |
RING_FORCE_TO_NONPRIV_RANGE_4);
}

static void cnl_whitelist_build(struct i915_wa_list *w)
static void cnl_whitelist_build(struct intel_engine_cs *engine)
{
struct i915_wa_list *w = &engine->whitelist;

if (engine->class != RENDER_CLASS)
return;

/* WaEnablePreemptionGranularityControlByUMD:cnl */
whitelist_reg(w, GEN8_CS_CHICKEN1);
}

static void icl_whitelist_build(struct i915_wa_list *w)
static void icl_whitelist_build(struct intel_engine_cs *engine)
{
/* WaAllowUMDToModifyHalfSliceChicken7:icl */
whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
struct i915_wa_list *w = &engine->whitelist;

/* WaAllowUMDToModifySamplerMode:icl */
whitelist_reg(w, GEN10_SAMPLER_MODE);
switch (engine->class) {
case RENDER_CLASS:
/* WaAllowUMDToModifyHalfSliceChicken7:icl */
whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);

/* WaEnableStateCacheRedirectToCS:icl */
whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
/* WaAllowUMDToModifySamplerMode:icl */
whitelist_reg(w, GEN10_SAMPLER_MODE);

/* WaEnableStateCacheRedirectToCS:icl */
whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);

/*
* WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
*
* This covers 4 register which are next to one another :
* - PS_INVOCATION_COUNT
* - PS_INVOCATION_COUNT_UDW
* - PS_DEPTH_COUNT
* - PS_DEPTH_COUNT_UDW
*/
whitelist_reg_ext(w, PS_INVOCATION_COUNT,
RING_FORCE_TO_NONPRIV_RD |
RING_FORCE_TO_NONPRIV_RANGE_4);
break;

case VIDEO_DECODE_CLASS:
/* hucStatusRegOffset */
whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
RING_FORCE_TO_NONPRIV_RD);
/* hucUKernelHdrInfoRegOffset */
whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
RING_FORCE_TO_NONPRIV_RD);
/* hucStatus2RegOffset */
whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
RING_FORCE_TO_NONPRIV_RD);
break;

default:
break;
}
}

void intel_engine_init_whitelist(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
struct i915_wa_list *w = &engine->whitelist;

GEM_BUG_ON(engine->id != RCS0);

wa_init_start(w, "whitelist");

if (IS_GEN(i915, 11))
icl_whitelist_build(w);
icl_whitelist_build(engine);
else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(w);
cnl_whitelist_build(engine);
else if (IS_COFFEELAKE(i915))
cfl_whitelist_build(w);
cfl_whitelist_build(engine);
else if (IS_GEMINILAKE(i915))
glk_whitelist_build(w);
glk_whitelist_build(engine);
else if (IS_KABYLAKE(i915))
kbl_whitelist_build(w);
kbl_whitelist_build(engine);
else if (IS_BROXTON(i915))
bxt_whitelist_build(w);
bxt_whitelist_build(engine);
else if (IS_SKYLAKE(i915))
skl_whitelist_build(w);
skl_whitelist_build(engine);
else if (INTEL_GEN(i915) <= 8)
return;
else
Expand Down Expand Up @@ -1167,8 +1247,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
wa_write_or(wal,
GEN7_SARCHKMD,
GEN7_DISABLE_DEMAND_PREFETCH |
GEN7_DISABLE_SAMPLER_PREFETCH);
GEN7_DISABLE_DEMAND_PREFETCH);

/* Wa_1606682166:icl */
wa_write_or(wal,
GEN7_SARCHKMD,
GEN7_DISABLE_SAMPLER_PREFETCH);
}

if (IS_GEN_RANGE(i915, 9, 11)) {
Expand Down

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