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Add support for flashing boards #189
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What I understood yet (for validation):
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Did something working with: |
Hi @zguig52, thanks for looking at this. Linux-on-LiteX-VexRiscv is heavily relying on LiteX-Boards (https://github.com/litex-hub/litex-boards) and we should probably add the flash support there by adding a |
After some digging on the net, I see that there was a pull request related here: |
I did some tests with current code for flashing through OpenOCD, with the svf file coming from @ilya-epifanov (from previous pull requests). I saw that he was also in charge of most of OpenOCD script associated. Debug: 135 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_flash bank spi0 jtagspi 0 0 0 0 ecp5.spi0.proxy 0x32 Did some tests also just to flash the svf file, by commenting the specific lines where defining the target and had errors on reset halt command: |
Maybe I'm wrong somewhere or not understood everything, but with an ECP5 (and unlike xilinx or intel) a bridge loaded in RAM in not required. |
@trabucayre Is correct the ECP5 JTAG logic contains a command that enables pass-through to the FLASH pins, so you don't have to load a bridge bitstream. It is possible to use openOCD + a crafted SVF file. But it's quite slow, as the standard SVF protocol does not support conditional loops/branching. So after each page write and sector erase you really need to wait the maximum time as highlighted in your flash datasheet. I have an example of python script that creates a flat SVF here: https://gist.github.com/gregdavill/4f9f536757966171ef974f98348bbacb I also wrote a simple tool: https://github.com/gregdavill/ecpprog and I believe that openFPGALoader also works to perform FLASH writes through the JTAG interface with FT232H based programmers. This approach is much faster because the busy flag in the flash is polled, so erase/write times are closer to typical values, rather than max. |
@gregdavill true: openFPGALoader is able to perform FLASH writes with any JTAG compatible device |
True again. But it's not limited to the flash: each time a wait until status bit is (un)set, SVF add a delay instead of polling for the bit. |
Thanks @trabucayre, @gregdavill for the info/feedback. So let's forget OpenOCD for flashing on ECP5 then, @zguig52 we could switch the ECPIX5 to openFPGALoader or ecpprog and I'll do a pass on the different LiteX-Boards later to be sure we have flashing support for most of the supported boards. |
Hi, thanks all for the reply and support. I did a quick survey on openFPGALoader capabilities yet WRT litex-boards. Native supported boards:
Supported FPGA:
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Here the quickly done compatibility matrix (to be checked / validated / ...) |
Best would be to have a one tool fit all, but not sure it will be possible. Maybe the best is to put a layer of abstraction in linux on vexrisc build / flash functions (as it seems to be already ?). Then only the list of requirements might be different depending on the board (openocd / openfpgaloader / ...). Related to OpenFPGALoader VS ecpprog, what are the major pro and cons that you would see related to each solution? As I understood / saw, there are 3 main operations to be done:
What do you think to keep the following operations and add this new one with this prototype:
Other point I would like to discuss is about the build output files gateware names, I think it might be useful to add to the file name the configuration associated (or a subfolder for each conf) to the build to avoid always having to rebuild when parameters are changing (when changing the CPU count for ex, and so on). |
In fact each boards already comes with a default programmer. So it's not really an issue if the same programmer is not used for all boards, but we should still try to be consistent and avoid using too much different programmers. For Xilinx FPGA, OpenOCD is working fine and we are also using it for JTAG UART, so we are going to keep it, but for Lattice, Intel and others we could eventually change. Not sure we should keep OpenOCD to load the gateware if another programmer will be used for Flashing. For the operations, you are right. The current For the build name, we could indeed add at least add the cpu count to it (ex ecpix5_cc1, ecpix5_cc2, etc... as done for the VexRiscv cluster name) and eventually extend it to others parameters in the future. |
OK great! Still a few questions:
Shall we first manage the "flash_gateware" operation with current functions prototype (flash with offset 0), and flash_firmware with a specific offset or shall we go directly to 2 different functions prototypes (as there is a big coupling to all boards files to be reviewed)? |
Thanks for my "order list" :)
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@zguig52 We should probably first make sure we can provide a |
@enjoy-digital - Sadly, as OpenFPGALoader is licensed under the AGPL a large number of people contributing to this repository can not use the software (or even look at the software), hence we will need to support an alternative tool as well. |
What is the best license and the way to change this? |
@trabucayre -- Changing the license of a project which has been accepting contributions but not using a CLA is a fairly complicated process which is not guaranteed to be successful (see the original GCC OpenRISC support issue). I would be happy to walk you through the process. |
Yes of course! |
@enjoy-digital I did commits to add flash to ECPIX5 board only so you can have a check if this is what you were expecting in terms of implementation. If this is what you were expecting, I can also take in charge to add this function to all ECP5 boards, no problem (and maybe others that have not yet this method and that are supported by OpenFPGALoader) |
@mithro, what is the issue with AGPL licence use? Here we only call the binary file to load code, so like a proprietary software, the license is not "propagated", isn't it? When reading the AGPL licence, there is something, but only related to network usage of the software. I don't think we are in this use case. @trabucayre , best licenses to support use in both free and proprietary software are MIT / BSD from what I know. It literally doesn't oblige anybody to contribute and this comes only from free will (to the contrary of GPL). Do you agree @mithro ? |
Closing since no update. The general direction for this repository if to reuse as much as possible from LiteX and LiteX-boards repository. So boards with flashing directly supported in LiteX-Boards will also be directly supported here. |
Hi guys,
I'm working on flashspi and board ECPIX5. I had first an issue with specific clock pin as described here: YosysHQ/prjtrellis#158
I finished by just removing the associated core clk pinout and have this finally:
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("AA2")),
Subsignal("mosi", Pins("AE2")),
Subsignal("miso", Pins("AD2")),
Subsignal("wp", Pins("AF2")),
Subsignal("hold", Pins("AE1")),
IOStandard("LVCMOS33")
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("AA2")),
Subsignal("dq", Pins("AE2", "AD2", "AF2", "AE1")),
IOStandard("LVCMOS33")
),
Is it the right way to do?
Second, now I would like to flash the FPGA config in it and saw that the make.py --flash is to be done in project linux on vexrisc. Have you a few guidelines/conclusions on how is planned to be implemented this function so I can try to do it?
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