HV: update ept address range for pre-launched VM

For a pre-launched VM, a region from PTDEV_HI_MMIO_START is used to store 64bit vBARs of PT devices which address is high than 4G. The region should be located after all user memory space and be coverd by guest EPT address. Tracked-On: projectacrn#4458 Signed-off-by: Victor Sun <victor.sun@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
liuwei987 · Mar 12, 2020 · a68f655 · a68f655
1 parent e745534
commit a68f655
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Showing 7 changed files with 27 additions and 10 deletions.
diff --git a/hypervisor/arch/x86/configs/apl-mrb/pci_devices.h b/hypervisor/arch/x86/configs/apl-mrb/pci_devices.h
@@ -7,6 +7,8 @@
 #ifndef PCI_DEVICES_H_
 #define PCI_DEVICES_H_
 
+#define PTDEV_HI_MMIO_SIZE	0UL
+
 #define SATA_CONTROLLER_0	.pbdf.bits = {.b = 0x00U, .d = 0x12U, .f = 0x00U},	\
 				.vbar_base[0] = 0xb3f10000UL,				\
 				.vbar_base[1] = 0xb3f53000UL,				\

diff --git a/hypervisor/arch/x86/configs/dnv-cb2/pci_devices.h b/hypervisor/arch/x86/configs/dnv-cb2/pci_devices.h
@@ -7,6 +7,8 @@
 #ifndef PCI_DEVICES_H_
 #define PCI_DEVICES_H_
 
+#define PTDEV_HI_MMIO_SIZE	0UL
+
 #define SATA_CONTROLLER_0	.pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U}
 #define USB_CONTROLLER_0	.pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x00U}
 #define ETHERNET_CONTROLLER_0	.pbdf.bits = {.b = 0x03U, .d = 0x00U, .f = 0x00U}

diff --git a/hypervisor/arch/x86/configs/nuc7i7dnb/pci_devices.h b/hypervisor/arch/x86/configs/nuc7i7dnb/pci_devices.h
@@ -7,18 +7,20 @@
 #ifndef PCI_DEVICES_H_
 #define PCI_DEVICES_H_
 
+#define PTDEV_HI_MMIO_SIZE	0xe00000UL
+
 #define SATA_CONTROLLER_0	.pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U},	\
-				.vbar_base[0] = 0xdf248000UL, 				\
-				.vbar_base[1] = 0xdf24c000UL,				\
-				.vbar_base[5] = 0xdf24b000UL
+				.vbar_base[0] = PTDEV_HI_MMIO_START + 0x200000UL, 	\
+				.vbar_base[1] = PTDEV_HI_MMIO_START + 0x400000UL,	\
+				.vbar_base[5] = PTDEV_HI_MMIO_START + 0x600000UL
 
 #define USB_CONTROLLER_0	.pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U}, 	\
-				.vbar_base[0] = 0xdf230000UL
+				.vbar_base[0] = PTDEV_HI_MMIO_START + 0x800000UL
 
 #define ETHERNET_CONTROLLER_0	.pbdf.bits = {.b = 0x00U, .d = 0x1fU, .f = 0x06U},	\
-				.vbar_base[0] = 0xdf200000UL
+				.vbar_base[0] = PTDEV_HI_MMIO_START + 0xa00000UL
 
 #define NETWORK_CONTROLLER_0	.pbdf.bits = {.b = 0x01U, .d = 0x00U, .f = 0x00U},	\
-				.vbar_base[0] = 0xdf100000UL
+				.vbar_base[0] = PTDEV_HI_MMIO_START + 0xc00000UL
 
 #endif /* PCI_DEVICES_H_ */
diff --git a/hypervisor/arch/x86/configs/whl-ipc-i5/pci_devices.h b/hypervisor/arch/x86/configs/whl-ipc-i5/pci_devices.h
@@ -20,6 +20,8 @@
 #ifndef PCI_DEVICES_H_
 #define PCI_DEVICES_H_
 
+#define PTDEV_HI_MMIO_SIZE			0UL
+
 #define HOST_BRIDGE                             .pbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U}
 #define VGA_COMPATIBLE_CONTROLLER_0             .pbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U}, \
                                                 .vbar_base[0] = 0xa0000000UL, \

diff --git a/hypervisor/arch/x86/page.c b/hypervisor/arch/x86/page.c
@@ -83,10 +83,10 @@ static struct page sos_vm_pd_pages[SOS_VM_NUM][PD_PAGE_NUM(EPT_ADDRESS_SPACE(CON
 static struct page sos_vm_pt_pages[SOS_VM_NUM][PT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE))];
 
 /* pre_uos_nworld_pml4_pages */
-static struct page pre_uos_nworld_pml4_pages[PRE_VM_NUM][PML4_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
-static struct page pre_uos_nworld_pdpt_pages[PRE_VM_NUM][PDPT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
-static struct page pre_uos_nworld_pd_pages[PRE_VM_NUM][PD_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
-static struct page pre_uos_nworld_pt_pages[PRE_VM_NUM][PT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
+static struct page pre_uos_nworld_pml4_pages[PRE_VM_NUM][PML4_PAGE_NUM(PRE_VM_EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
+static struct page pre_uos_nworld_pdpt_pages[PRE_VM_NUM][PDPT_PAGE_NUM(PRE_VM_EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
+static struct page pre_uos_nworld_pd_pages[PRE_VM_NUM][PD_PAGE_NUM(PRE_VM_EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
+static struct page pre_uos_nworld_pt_pages[PRE_VM_NUM][PT_PAGE_NUM(PRE_VM_EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
 
 /* post_uos_nworld_pml4_pages */
 static struct page post_uos_nworld_pml4_pages[MAX_POST_VM_NUM][PML4_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];

diff --git a/hypervisor/include/arch/x86/page.h b/hypervisor/include/arch/x86/page.h
@@ -7,6 +7,8 @@
 #ifndef PAGE_H
 #define PAGE_H
 
+#include <pci_devices.h>
+
 #define PAGE_SHIFT	12U
 #define PAGE_SIZE	(1U << PAGE_SHIFT)
 #define PAGE_MASK	0xFFFFFFFFFFFFF000UL
@@ -33,6 +35,11 @@
 			((size) + PLATFORM_LO_MMIO_SIZE + PLATFORM_HI_MMIO_SIZE)	\
 			: (MEM_2G + PLATFORM_LO_MMIO_SIZE + PLATFORM_HI_MMIO_SIZE))
 
+#define PTDEV_HI_MMIO_START		((CONFIG_UOS_RAM_SIZE > MEM_2G) ?	\
+			(CONFIG_UOS_RAM_SIZE + PLATFORM_LO_MMIO_SIZE) : (MEM_2G + PLATFORM_LO_MMIO_SIZE))
+
+#define PRE_VM_EPT_ADDRESS_SPACE(size)	(PTDEV_HI_MMIO_START + PTDEV_HI_MMIO_SIZE)
+
 #define TRUSTY_PML4_PAGE_NUM(size)	(1UL)
 #define TRUSTY_PDPT_PAGE_NUM(size)	(1UL)
 #define TRUSTY_PD_PAGE_NUM(size)	(PD_PAGE_NUM(size))

diff --git a/hypervisor/scenarios/logical_partition/pci_dev.c b/hypervisor/scenarios/logical_partition/pci_dev.c
@@ -7,6 +7,8 @@
 #include <vm_config.h>
 #include <pci_devices.h>
 #include <vpci.h>
+#include <mmu.h>
+#include <page.h>
 
 /* The vbar_base info of pt devices is included in device MACROs which defined in
  *           arch/x86/configs/$(CONFIG_BOARD)/pci_devices.h.