[FIRTOOL] More sane chisel interface directory handling (#6687)

Deal with a few more situations when outputting chisel interfaces.
llvm · Feb 21, 2024 · 5544820 · 5544820
1 parent e8f4f34
commit 5544820
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diff --git a/lib/Firtool/Firtool.cpp b/lib/Firtool/Firtool.cpp
@@ -80,11 +80,14 @@ LogicalResult firtool::populateCHIRRTLToLowFIRRTL(mlir::PassManager &pm,
   pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInferResetsPass());
 
   if (opt.shouldExportChiselInterface()) {
-    if (opt.getChiselInterfaceOutputDirectory().empty()) {
+    StringRef outdir = opt.getChiselInterfaceOutputDirectory();
+    if (opt.isDefaultOutputFilename() && outdir.empty()) {
       pm.nest<firrtl::CircuitOp>().addPass(createExportChiselInterfacePass());
     } else {
-      pm.nest<firrtl::CircuitOp>().addPass(createExportSplitChiselInterfacePass(
-          opt.getChiselInterfaceOutputDirectory()));
+      if (outdir.empty())
+        outdir = opt.getOutputFilename();
+      pm.nest<firrtl::CircuitOp>().addPass(
+          createExportSplitChiselInterfacePass(outdir));
     }
   }
 

diff --git a/test/firtool/chisel-interface.fir b/test/firtool/chisel-interface.fir
@@ -5,6 +5,10 @@
 ; RUN: firtool %s --disable-output --export-chisel-interface --chisel-interface-out-dir %t
 ; RUN: FileCheck %s -input-file=%t/Foo.scala
 
+; Test exporting a Chisel interface to the default directory.
+; RUN: firtool %s --split-verilog --export-chisel-interface -o %t
+; RUN: FileCheck %s -input-file=%t/Foo.scala
+
 ; CHECK-LABEL: // Generated by CIRCT
 ; CHECK-LABEL: package shelf.foo
 ; CHECK-LABEL: import chisel3._