[FIRRTL] (dshr) unsign mismatch

[drom]

The following FIRRTL program

circuit top_mod :
  module top_mod :
    input inp_4: SInt<6>
    input tmp7: UInt<1>
    output tmp13: UInt<1>
    tmp13 <= dshr(tmp7, asUInt(inp_4))

Compiled with firtool --lower-to-rtl produces this Verilog:

module top_mod(
  input  [5:0] inp_4,
  input        tmp7,
  output       tmp13);

  assign tmp13 = tmp7 >> inp_4[0];	// a_top_mod.fir:2:3, :6:14
endmodule

Compiled with firrtl-1.4.0 produces this Verilog:

module top_mod(
  input  [5:0] inp_4,
  input        tmp7,
  output       tmp13
);
  assign tmp13 = tmp7 >> inp_4;
endmodule

Yosys (Yosys 0.9+3755 (git sha1 442d19f6, clang 11.0.0 -fPIC -Os)) reports formal mismatch:

ERROR: Found 1 unproven $equiv cells in 'equiv_status -assert'.

[lattner]

Fixed in d2fd8fc, thanks!