[SVExtractTestCode] Instance inlining doesn't update inner symbols and clone sv.bind

[uenoku]

circuit Top:
  module Assert:
    input clock: Clock
    input a: UInt<1>
    assert(clock, a, a, "foo")

  module Top:
    input clock: Clock
    input a: UInt<1>
    input b: UInt<1>
    inst a1 of Assert
    a1.a <= a
    a1.clock <= clock
    inst a2 of Assert
    a2.a <= b
    a2.clock <= clock

The current output with firtool -extract-test-code.

// Generated by CIRCT firtool-1.48.0-44-gf453a87cd
// VCS coverage exclude_file
module Assert_assert(
  input a,
        clock
);

  always @(posedge clock) begin
    if (a)
      assert(a) else $error("foo");
  end // always @(posedge)
endmodule

module Top(
  input clock,
        a,
        b
);

endmodule


// ----- 8< ----- FILE "bindfile.sv" ----- 8< -----

// Generated by CIRCT firtool-1.48.0-44-gf453a87cd
bind Top Assert_assert Assert_assert (
  .a     (a),
  .clock (clock)
);

The second assertion is not emitted in the bind file. This is because bind op is not cloned properly when input only modules are inlined and the first instance (in the instance graph ndoe iterator) is preserved. This bug was first introduced by 0d5cf22 which was included in 1.17.0.

[uenoku]

Another example

circuit Top:
  module Assert:
    input clock: Clock
    input a: UInt<1>
    assert(clock, a, a, "foo")

  module Assert_wrapper:
    input clock: Clock
    input a: UInt<1>
    output b: UInt<1>
    inst as of Assert 
    as.a <= a
    as.clock <= clock
    b <= a

  module Top:
    input clock: Clock
    input a: UInt<1>
    input b: UInt<1>
    output c: UInt<1>
    inst a1 of Assert_wrapper
    a1.a <= a
    a1.clock <= clock
    inst a2 of Assert
    a2.a <= b
    a2.clock <= clock
    c <= a1.b