[Seq][FIRRTL] Add a seq.clock type to carry clocks for seq.firreg and seq.firmem

[nandor]

Presently, in the firtool pipeline, clock information is thrown away when !firrtl.clock is lowered to i1. This is sub-optimal since past the lowering to HW, it is difficult to reason about the sanity of clocking in the design. For example, constant or invalid clocks require a data-flow analysis to find, instead of simply locating FIRRTL AsClock primitives. To address the shortcomings of hw, the firtool flow should preserve clock information up until the lowering of seq to sv.

seq should be equippend with a seq.clock type, to be used by the following ops:

• seq.firreg
• seq.firmem
• seq.clock_gate

Additionally, seq.from_clock and seq.to_clock ops should cast between clocks and i1.

[nandor]

The newly opened PRs switch over ARC and firtool to use the clock type. Registers shared with other dialects allow the use of both i1 and seq.clock for clocking. This is a temporary measure until all dialects are switched over.