[Seq] Merge Seq-to-SV lowering passes #5901
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Looks like there's an unintended LLVM bump in here https://github.com/llvm/circt/pull/5901/files#diff-ef5a927f5a4ae8bdfa7d187079fa7b2aabc8d72ce219c564f78c9498ff59d2f9 |
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Sorry about that, should have rebased unto master after bumping LLVM. |
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fabianschuiki
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Aug 22, 2023
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LGTM! Thanks for merging these passes. Does this fix #5639?
The pattern rewriter can be applied alongside the FIR register lowering transforms to eliminate the need for two separate passes.
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Not fully. Some FIFO or HLMem lowerings remain. |
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The pattern rewriter can be applied alongside the FIR register lowering transforms to eliminate the need for two separate passes.
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The pattern rewriter can be applied alongside the FIR register lowering transforms to eliminate the need for two separate passes.
This is done in order to create a centralized place where all clock ops that will use a dedicated clock time will be lowered (See #5851).