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[Comb][FIRRTL][Seq] Fix fusing locations to append not add as metadata. #5349

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merged 2 commits into from
Jun 9, 2023
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[Comb][FIRRTL][Seq] Fix fusing locations to append not add as metadata. #5349

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deb66c6
[FIRRTL][Seq] Fix fusing locations to append not add as metadata.
dtzSiFive Jun 9, 2023
a51ab34
[Comb] Similarly fix FusedLoc creation.
dtzSiFive Jun 9, 2023
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2 changes: 1 addition & 1 deletion lib/Dialect/FIRRTL/Transforms/IMConstProp.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -878,7 +878,7 @@ void IMConstPropPass::rewriteModuleBody(FModuleOp module) {
if (constIt != constPool.end()) {
auto *cst = constIt->second;
// Add location to the constant
cst->setLoc(builder.getFusedLoc(cst->getLoc(), loc));
cst->setLoc(builder.getFusedLoc({cst->getLoc(), loc}));
return cst->getResult(0);
}
auto savedIP = builder.saveInsertionPoint();
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2 changes: 1 addition & 1 deletion lib/Dialect/Seq/Transforms/LowerSeqToSV.cpp
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Expand Up @@ -184,7 +184,7 @@ class FirRegLower {
OpBuilder builder(module.getBody());
auto &constant = constantCache[value];
if (constant) {
constant->setLoc(builder.getFusedLoc(constant->getLoc(), loc));
constant->setLoc(builder.getFusedLoc({constant->getLoc(), loc}));
return constant;
}

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33 changes: 33 additions & 0 deletions test/Dialect/FIRRTL/imcp-locations.mlir
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@@ -0,0 +1,33 @@
// RUN: circt-opt -pass-pipeline='builtin.module(firrtl.circuit(firrtl-imconstprop))' --mlir-print-local-scope --mlir-print-debuginfo %s | FileCheck %s

// CHECK-LABEL: circuit "Test"
firrtl.circuit "Test" {
firrtl.module private @Consts(out %c2 : !firrtl.uint<3>, out %c4 : !firrtl.uint<3>) {
%c2_ui3 = firrtl.constant 2 : !firrtl.uint<3>
%c4_ui3 = firrtl.constant 4 : !firrtl.uint<3>
firrtl.strictconnect %c2, %c2_ui3 : !firrtl.uint<3>
firrtl.strictconnect %c4, %c4_ui3 : !firrtl.uint<3>
}
// CHECK-LABEL: module @Test
firrtl.module @Test() {
// CHECK-NEXT: %[[SIX:.+]] = firrtl.constant 6 : !firrtl.uint<3>
// CHECK-SAME: loc(fused["test.txt":5:2, "test.txt":4:2])

%c2, %c4 = firrtl.instance consts @Consts(out c2: !firrtl.uint<3>, out c4: !firrtl.uint<3>)

%w_or = firrtl.wire : !firrtl.uint<3> loc("test.txt":4:2)
%w_add = firrtl.wire : !firrtl.uint<3> loc("test.txt":5:2)

%or = firrtl.or %c2, %c4: (!firrtl.uint<3>, !firrtl.uint<3>) -> !firrtl.uint<3>
%add = firrtl.add %c2, %c4: (!firrtl.uint<3>, !firrtl.uint<3>) -> !firrtl.uint<4>
%addtrunc = firrtl.bits %add 2 to 0 : (!firrtl.uint<4>) -> !firrtl.uint<3>

firrtl.strictconnect %w_or, %or : !firrtl.uint<3>
firrtl.strictconnect %w_add, %addtrunc : !firrtl.uint<3>

// CHECK: %n_or = firrtl.node sym @n_or %[[SIX]]
// CHECK: %n_add = firrtl.node sym @n_add %[[SIX]]
%n_or = firrtl.node sym @n_or %w_or : !firrtl.uint<3>
%n_add = firrtl.node sym @n_add %w_add : !firrtl.uint<3>
}
}