[Seq] Canonicalize transitive clock gates #5504
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This adds a folder for clock gates which removes clock gates that are transitively enable'd by other clock gates in a clock gate hierarchy.
fabianschuiki
approved these changes
Jun 28, 2023
lib/Dialect/Seq/SeqOps.cpp
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Comment on lines
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727
| // Transitive clock gating - eliminate clock gates that are driven by an | ||
| // identical enable signal somewhere in a clock gate hierarchy. | ||
| auto clockGateInput = getInput().getDefiningOp<ClockGateOp>(); | ||
| while (clockGateInput) { | ||
| if (clockGateInput.getEnable() == getEnable()) | ||
| return getInput(); | ||
| clockGateInput = clockGateInput.getInput().getDefiningOp<ClockGateOp>(); | ||
| } |
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I think you also need to check the test_enable here.
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hmm... would it then be correct to OR the test_enable of the current clock gate with the TE of the upstream matching clock gate?
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Yeah I think you could also do that! Or just check if the test enables also agree, not just the regular enable. I'd expect in most designs there is no test enable, or if there is one, it's all connected to one single signal almost everywhere in the hierarchy. So you might not be losing much if you just check for it instead of creating a new comb.or 😃
teqdruid
approved these changes
Jun 28, 2023
lib/Dialect/Seq/SeqOps.cpp
Outdated
| @@ -717,6 +717,15 @@ OpFoldResult ClockGateOp::fold(FoldAdaptor adaptor) { | |||
| if (isConstantZero(adaptor.getInput())) | |||
| return IntegerAttr::get(IntegerType::get(getContext(), 1), 0); | |||
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| // Transitive clock gating - eliminate clock gates that are driven by an | |||
| // identical enable signal somewhere in a clock gate hierarchy. | |||
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nit: "... somewhere higher in the clock..."
calebmkim
pushed a commit
to andrewb1999/circt
that referenced
this pull request
Jul 12, 2023
This adds a folder for clock gates which removes clock gates that are transitively enable'd by other clock gates in a clock gate hierarchy.
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This adds a folder for clock gates which removes clock gates that are transitively enable'd by other clock gates in a clock gate hierarchy.