[ImportVerilog] Add if and loop statements #6831
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Extend the `ImportVerilog` conversion to support `if` statements and `for`, `repeat`, `while`, `do ... while`, and `forever` loops. Lower them to `scf.if` and `scf.while` ops for now. In the future, since Verilog has `break`, `continue`, and `return` statements, we may have to switch to a different dialect or defined these ops in the Moore dialect. Co-authored-by: Hailong Sun <hailong.sun@terapines.com> Co-authored-by: ShiZuoye <albertethon@163.com> Co-authored-by: hunterzju <hunter_ht@zju.edu.cn> Co-authored-by: Anqi Yu <anqi.yu@terapines.com>
hailongSun2000
approved these changes
Mar 15, 2024
| // CHECK: } do { | ||
| // CHECK: scf.yield | ||
| // CHECK: } | ||
| do x = y; while (x); |
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I think the moore.blocking_assign %x, %y should occur in the "after" region, like do{ moore.blocking_assign %x, %y}.
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Sorry about that, I mixed the concept with the while and do-while 😅.
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Yeah the naming in scf is a bit adventurous at times 😁
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Extend the
ImportVerilogconversion to supportifstatements andfor,repeat,while,do ... while, andforeverloops. Lower them toscf.ifandscf.whileops for now. In the future, since Verilog hasbreak,continue, andreturnstatements, we may have to switch to a different dialect or defined these ops in the Moore dialect.