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[ImportVerilog] Fix unknown name caused by local variables. #6995

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merged 1 commit into from
May 8, 2024

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hailongSun2000
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If we don't collect the local temporary variables, it triggers the following error:
For example:

module Temporary();
  int x, y, z;
  always_comb begin
    automatic int a;
    a = x + 1;
    y = a;
    a = a + 1;
    z = a;
  end
endmodule
Temporary.sv:5:5: error: unknown name `a`
    a = x + 1;

@hailongSun2000 hailongSun2000 added the Verilog/SystemVerilog Involving a Verilog dialect label May 7, 2024
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@uenoku uenoku left a comment

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LGTM! Could you add a test?

@hailongSun2000
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LGTM! Could you add a test?

No problem! But I'll wait to add it tomorrow. And the IR is the same as non-local variables.

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@fabianschuiki fabianschuiki left a comment

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Thanks for the fix! I agree with @uenoku: once there's a test this is good to go 😃

@hailongSun2000
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Thanks for the fix! I agree with @uenoku: once there's a test this is good to go 😃

I have added the test cases.

@hailongSun2000
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LGTM! Could you add a test?

I have added the test cases.

@hailongSun2000 hailongSun2000 merged commit 06cb84a into llvm:main May 8, 2024
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@hailongSun2000 hailongSun2000 deleted the hailong/fix-unknown-name branch July 4, 2024 06:27
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3 participants