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mve-vecreduce-addpred.ll
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mve-vecreduce-addpred.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x, <4 x i32> %b) {
; CHECK-LABEL: add_v4i32_v4i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vaddvt.u32 r0, q0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <4 x i32> %b, zeroinitializer
%s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
ret i32 %z
}
define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_zext(<4 x i32> %x, <4 x i32> %b) {
; CHECK-LABEL: add_v4i32_v4i64_zext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vaddlvt.u32 r0, r1, q0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <4 x i32> %b, zeroinitializer
%xx = zext <4 x i32> %x to <4 x i64>
%s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)
ret i64 %z
}
define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_sext(<4 x i32> %x, <4 x i32> %b) {
; CHECK-LABEL: add_v4i32_v4i64_sext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vaddlvt.s32 r0, r1, q0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <4 x i32> %b, zeroinitializer
%xx = sext <4 x i32> %x to <4 x i64>
%s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)
ret i64 %z
}
define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_zext(<2 x i32> %x, <2 x i32> %b) {
; CHECK-LABEL: add_v2i32_v2i64_zext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmov.i64 q2, #0xffffffff
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <2 x i32> %b, zeroinitializer
%xx = zext <2 x i32> %x to <2 x i64>
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
ret i64 %z
}
define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_sext(<2 x i32> %x, <2 x i32> %b) {
; CHECK-LABEL: add_v2i32_v2i64_sext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: asrs r0, r0, #31
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: asrs r0, r0, #31
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: vand q0, q2, q0
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <2 x i32> %b, zeroinitializer
%xx = sext <2 x i32> %x to <2 x i64>
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
ret i64 %z
}
define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_zext(<8 x i16> %x, <8 x i16> %b) {
; CHECK-LABEL: add_v8i16_v8i32_zext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vaddvt.u16 r0, q0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <8 x i16> %b, zeroinitializer
%xx = zext <8 x i16> %x to <8 x i32>
%s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)
ret i32 %z
}
define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_sext(<8 x i16> %x, <8 x i16> %b) {
; CHECK-LABEL: add_v8i16_v8i32_sext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vaddvt.s16 r0, q0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <8 x i16> %b, zeroinitializer
%xx = sext <8 x i16> %x to <8 x i32>
%s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)
ret i32 %z
}
define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_zext(<4 x i16> %x, <4 x i16> %b) {
; CHECK-LABEL: add_v4i16_v4i32_zext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u16 q0, q0
; CHECK-NEXT: vmovlb.u16 q1, q1
; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vaddvt.u32 r0, q0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <4 x i16> %b, zeroinitializer
%xx = zext <4 x i16> %x to <4 x i32>
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
ret i32 %z
}
define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_sext(<4 x i16> %x, <4 x i16> %b) {
; CHECK-LABEL: add_v4i16_v4i32_sext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vmovlb.u16 q1, q1
; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vaddvt.u32 r0, q0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <4 x i16> %b, zeroinitializer
%xx = sext <4 x i16> %x to <4 x i32>
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
ret i32 %z
}
define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16(<8 x i16> %x, <8 x i16> %b) {
; CHECK-LABEL: add_v8i16_v8i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vaddvt.u16 r0, q0
; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <8 x i16> %b, zeroinitializer
%s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> zeroinitializer
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)
ret i16 %z
}
define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_zext(<8 x i16> %x, <8 x i16> %b) {
; CHECK-LABEL: add_v8i16_v8i64_zext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov.i8 q2, #0x0
; CHECK-NEXT: vmov.i8 q3, #0xff
; CHECK-NEXT: vcmp.i16 eq, q1, zr
; CHECK-NEXT: vpsel q2, q3, q2
; CHECK-NEXT: vmov.u16 r0, q2[0]
; CHECK-NEXT: vmov.32 q1[0], r0
; CHECK-NEXT: vmov.u16 r0, q2[1]
; CHECK-NEXT: vmov.32 q1[1], r0
; CHECK-NEXT: vmov.u16 r0, q2[2]
; CHECK-NEXT: vmov.32 q1[2], r0
; CHECK-NEXT: vmov.u16 r0, q2[3]
; CHECK-NEXT: vmov.32 q1[3], r0
; CHECK-NEXT: vcmp.i32 ne, q1, zr
; CHECK-NEXT: vmov.i64 q1, #0xffff
; CHECK-NEXT: vmrs r0, p0
; CHECK-NEXT: and r1, r0, #1
; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov.32 q3[0], r1
; CHECK-NEXT: vmov.32 q3[1], r1
; CHECK-NEXT: ubfx r1, r0, #4, #1
; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov.32 q3[2], r1
; CHECK-NEXT: vmov.32 q3[3], r1
; CHECK-NEXT: vmov.u16 r1, q0[0]
; CHECK-NEXT: vmov.32 q4[0], r1
; CHECK-NEXT: vmov.u16 r1, q0[1]
; CHECK-NEXT: vmov.32 q4[2], r1
; CHECK-NEXT: vand q4, q4, q1
; CHECK-NEXT: vand q3, q4, q3
; CHECK-NEXT: vmov r1, s15
; CHECK-NEXT: vmov r2, s13
; CHECK-NEXT: vmov r3, s12
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s14
; CHECK-NEXT: add r2, r3
; CHECK-NEXT: ubfx r3, r0, #8, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: ubfx r0, r0, #12, #1
; CHECK-NEXT: vmov.32 q3[0], r3
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmov.32 q3[1], r3
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vand q4, q4, q1
; CHECK-NEXT: vand q3, q4, q3
; CHECK-NEXT: vmov r3, s12
; CHECK-NEXT: vmov r0, s13
; CHECK-NEXT: adds r2, r2, r3
; CHECK-NEXT: vmov r3, s15
; CHECK-NEXT: adcs r1, r0
; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: adds.w r12, r2, r0
; CHECK-NEXT: vmov.u16 r2, q2[4]
; CHECK-NEXT: vmov.32 q3[0], r2
; CHECK-NEXT: vmov.u16 r2, q2[5]
; CHECK-NEXT: vmov.32 q3[1], r2
; CHECK-NEXT: vmov.u16 r2, q2[6]
; CHECK-NEXT: vmov.32 q3[2], r2
; CHECK-NEXT: vmov.u16 r2, q2[7]
; CHECK-NEXT: vmov.32 q3[3], r2
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: vcmp.i32 ne, q3, zr
; CHECK-NEXT: vmrs r2, p0
; CHECK-NEXT: and r3, r2, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q2[0], r3
; CHECK-NEXT: vmov.32 q2[1], r3
; CHECK-NEXT: ubfx r3, r2, #4, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q2[2], r3
; CHECK-NEXT: vmov.32 q2[3], r3
; CHECK-NEXT: vmov.u16 r3, q0[4]
; CHECK-NEXT: vmov.32 q3[0], r3
; CHECK-NEXT: vmov.u16 r3, q0[5]
; CHECK-NEXT: vmov.32 q3[2], r3
; CHECK-NEXT: vand q3, q3, q1
; CHECK-NEXT: vand q2, q3, q2
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov r3, s9
; CHECK-NEXT: adds.w r12, r12, r0
; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: vmov r3, s11
; CHECK-NEXT: adds.w r0, r0, r12
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: ubfx r3, r2, #8, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: ubfx r2, r2, #12, #1
; CHECK-NEXT: vmov.32 q2[0], r3
; CHECK-NEXT: rsbs r2, r2, #0
; CHECK-NEXT: vmov.32 q2[1], r3
; CHECK-NEXT: vmov.32 q2[2], r2
; CHECK-NEXT: vmov.32 q2[3], r2
; CHECK-NEXT: vmov.u16 r2, q0[6]
; CHECK-NEXT: vmov.32 q3[0], r2
; CHECK-NEXT: vmov.u16 r2, q0[7]
; CHECK-NEXT: vmov.32 q3[2], r2
; CHECK-NEXT: vand q0, q3, q1
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: vmov r2, s3
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <8 x i16> %b, zeroinitializer
%xx = zext <8 x i16> %x to <8 x i64>
%s = select <8 x i1> %c, <8 x i64> %xx, <8 x i64> zeroinitializer
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
ret i64 %z
}
define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_sext(<8 x i16> %x, <8 x i16> %b) {
; CHECK-LABEL: add_v8i16_v8i64_sext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i8 q2, #0x0
; CHECK-NEXT: vmov.i8 q3, #0xff
; CHECK-NEXT: vcmp.i16 eq, q1, zr
; CHECK-NEXT: vpsel q1, q3, q2
; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[1]
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[2]
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vcmp.i32 ne, q2, zr
; CHECK-NEXT: vmrs r0, p0
; CHECK-NEXT: and r1, r0, #1
; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov.32 q2[0], r1
; CHECK-NEXT: vmov.32 q2[1], r1
; CHECK-NEXT: ubfx r1, r0, #4, #1
; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov.32 q2[2], r1
; CHECK-NEXT: vmov.32 q2[3], r1
; CHECK-NEXT: vmov.u16 r1, q0[0]
; CHECK-NEXT: sxth r1, r1
; CHECK-NEXT: vmov.32 q3[0], r1
; CHECK-NEXT: asrs r1, r1, #31
; CHECK-NEXT: vmov.32 q3[1], r1
; CHECK-NEXT: vmov.u16 r1, q0[1]
; CHECK-NEXT: sxth r1, r1
; CHECK-NEXT: vmov.32 q3[2], r1
; CHECK-NEXT: asrs r1, r1, #31
; CHECK-NEXT: vmov.32 q3[3], r1
; CHECK-NEXT: vand q2, q3, q2
; CHECK-NEXT: vmov r1, s10
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov r12, s11
; CHECK-NEXT: vmov r3, s9
; CHECK-NEXT: adds r1, r1, r2
; CHECK-NEXT: adc.w r2, r3, r12
; CHECK-NEXT: ubfx r3, r0, #8, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: ubfx r0, r0, #12, #1
; CHECK-NEXT: vmov.32 q2[0], r3
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmov.32 q2[1], r3
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: asrs r0, r0, #31
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: asrs r0, r0, #31
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vand q2, q3, q2
; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: vmov r0, s9
; CHECK-NEXT: adds r1, r1, r3
; CHECK-NEXT: vmov r3, s11
; CHECK-NEXT: adcs r2, r0
; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: adds.w r12, r1, r0
; CHECK-NEXT: adc.w r1, r2, r3
; CHECK-NEXT: vmov.u16 r2, q1[4]
; CHECK-NEXT: vmov.32 q2[0], r2
; CHECK-NEXT: vmov.u16 r2, q1[5]
; CHECK-NEXT: vmov.32 q2[1], r2
; CHECK-NEXT: vmov.u16 r2, q1[6]
; CHECK-NEXT: vmov.32 q2[2], r2
; CHECK-NEXT: vmov.u16 r2, q1[7]
; CHECK-NEXT: vmov.32 q2[3], r2
; CHECK-NEXT: vcmp.i32 ne, q2, zr
; CHECK-NEXT: vmrs r2, p0
; CHECK-NEXT: and r3, r2, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q1[0], r3
; CHECK-NEXT: vmov.32 q1[1], r3
; CHECK-NEXT: ubfx r3, r2, #4, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q1[2], r3
; CHECK-NEXT: vmov.32 q1[3], r3
; CHECK-NEXT: vmov.u16 r3, q0[4]
; CHECK-NEXT: sxth r3, r3
; CHECK-NEXT: vmov.32 q2[0], r3
; CHECK-NEXT: asrs r3, r3, #31
; CHECK-NEXT: vmov.32 q2[1], r3
; CHECK-NEXT: vmov.u16 r3, q0[5]
; CHECK-NEXT: sxth r3, r3
; CHECK-NEXT: vmov.32 q2[2], r3
; CHECK-NEXT: asrs r3, r3, #31
; CHECK-NEXT: vmov.32 q2[3], r3
; CHECK-NEXT: vand q1, q2, q1
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmov r3, s5
; CHECK-NEXT: adds.w r12, r12, r0
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: vmov r3, s7
; CHECK-NEXT: adds.w r0, r0, r12
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: ubfx r3, r2, #8, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: ubfx r2, r2, #12, #1
; CHECK-NEXT: vmov.32 q1[0], r3
; CHECK-NEXT: rsbs r2, r2, #0
; CHECK-NEXT: vmov.32 q1[1], r3
; CHECK-NEXT: vmov.32 q1[2], r2
; CHECK-NEXT: vmov.32 q1[3], r2
; CHECK-NEXT: vmov.u16 r2, q0[6]
; CHECK-NEXT: sxth r2, r2
; CHECK-NEXT: vmov.32 q2[0], r2
; CHECK-NEXT: asrs r2, r2, #31
; CHECK-NEXT: vmov.32 q2[1], r2
; CHECK-NEXT: vmov.u16 r2, q0[7]
; CHECK-NEXT: sxth r2, r2
; CHECK-NEXT: vmov.32 q2[2], r2
; CHECK-NEXT: asrs r2, r2, #31
; CHECK-NEXT: vmov.32 q2[3], r2
; CHECK-NEXT: vand q0, q2, q1
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: vmov r2, s3
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <8 x i16> %b, zeroinitializer
%xx = sext <8 x i16> %x to <8 x i64>
%s = select <8 x i1> %c, <8 x i64> %xx, <8 x i64> zeroinitializer
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
ret i64 %z
}
define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_zext(<2 x i16> %x, <2 x i16> %b) {
; CHECK-LABEL: add_v2i16_v2i64_zext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i64 q2, #0xffff
; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vand q0, q0, q3
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: add r0, r1
; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <2 x i16> %b, zeroinitializer
%xx = zext <2 x i16> %x to <2 x i64>
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
ret i64 %z
}
define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_sext(<2 x i16> %x, <2 x i16> %b) {
; CHECK-LABEL: add_v2i16_v2i64_sext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q2, #0xffff
; CHECK-NEXT: vand q2, q1, q2
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q1[0], r0
; CHECK-NEXT: vmov.32 q1[1], r0
; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q1[2], r0
; CHECK-NEXT: vmov.32 q1[3], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: asrs r0, r0, #31
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: asrs r0, r0, #31
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vand q0, q2, q1
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <2 x i16> %b, zeroinitializer
%xx = sext <2 x i16> %x to <2 x i64>
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
ret i64 %z
}
define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_zext(<16 x i8> %x, <16 x i8> %b) {
; CHECK-LABEL: add_v16i8_v16i32_zext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i8 eq, q1, zr
; CHECK-NEXT: vaddvt.u8 r0, q0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <16 x i8> %b, zeroinitializer
%xx = zext <16 x i8> %x to <16 x i32>
%s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
ret i32 %z
}
define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_sext(<16 x i8> %x, <16 x i8> %b) {
; CHECK-LABEL: add_v16i8_v16i32_sext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i8 eq, q1, zr
; CHECK-NEXT: vaddvt.s8 r0, q0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <16 x i8> %b, zeroinitializer
%xx = sext <16 x i8> %x to <16 x i32>
%s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
ret i32 %z
}
define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_zext(<4 x i8> %x, <4 x i8> %b) {
; CHECK-LABEL: add_v4i8_v4i32_zext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q2, #0xff
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vaddvt.u32 r0, q0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <4 x i8> %b, zeroinitializer
%xx = zext <4 x i8> %x to <4 x i32>
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
ret i32 %z
}
define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_sext(<4 x i8> %x, <4 x i8> %b) {
; CHECK-LABEL: add_v4i8_v4i32_sext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vmov.i32 q2, #0xff
; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vaddvt.u32 r0, q0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <4 x i8> %b, zeroinitializer
%xx = sext <4 x i8> %x to <4 x i32>
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
ret i32 %z
}
define arm_aapcs_vfpcc zeroext i16 @add_v16i8_v16i16_zext(<16 x i8> %x, <16 x i8> %b) {
; CHECK-LABEL: add_v16i8_v16i16_zext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i8 eq, q1, zr
; CHECK-NEXT: vaddvt.u8 r0, q0
; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <16 x i8> %b, zeroinitializer
%xx = zext <16 x i8> %x to <16 x i16>
%s = select <16 x i1> %c, <16 x i16> %xx, <16 x i16> zeroinitializer
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)
ret i16 %z
}
define arm_aapcs_vfpcc signext i16 @add_v16i8_v16i16_sext(<16 x i8> %x, <16 x i8> %b) {
; CHECK-LABEL: add_v16i8_v16i16_sext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i8 eq, q1, zr
; CHECK-NEXT: vaddvt.s8 r0, q0
; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <16 x i8> %b, zeroinitializer
%xx = sext <16 x i8> %x to <16 x i16>
%s = select <16 x i1> %c, <16 x i16> %xx, <16 x i16> zeroinitializer
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)
ret i16 %z
}
define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_zext(<8 x i8> %x, <8 x i8> %b) {
; CHECK-LABEL: add_v8i8_v8i16_zext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u8 q0, q0
; CHECK-NEXT: vmovlb.u8 q1, q1
; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vaddvt.u16 r0, q0
; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <8 x i8> %b, zeroinitializer
%xx = zext <8 x i8> %x to <8 x i16>
%s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)
ret i16 %z
}
define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_sext(<8 x i8> %x, <8 x i8> %b) {
; CHECK-LABEL: add_v8i8_v8i16_sext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vmovlb.u8 q1, q1
; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vaddvt.u16 r0, q0
; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <8 x i8> %b, zeroinitializer
%xx = sext <8 x i8> %x to <8 x i16>
%s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)
ret i16 %z
}
define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8(<16 x i8> %x, <16 x i8> %b) {
; CHECK-LABEL: add_v16i8_v16i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vpt.i8 eq, q1, zr
; CHECK-NEXT: vaddvt.u8 r0, q0
; CHECK-NEXT: uxtb r0, r0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <16 x i8> %b, zeroinitializer
%s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> zeroinitializer
%z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %s)
ret i8 %z
}
define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_zext(<16 x i8> %x, <16 x i8> %b) {
; CHECK-LABEL: add_v16i8_v16i64_zext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vcmp.i8 eq, q1, zr
; CHECK-NEXT: vmov.i8 q2, #0x0
; CHECK-NEXT: vmov.i8 q3, #0xff
; CHECK-NEXT: vpsel q4, q3, q2
; CHECK-NEXT: vmov.u8 r0, q4[0]
; CHECK-NEXT: vmov.16 q1[0], r0
; CHECK-NEXT: vmov.u8 r0, q4[1]
; CHECK-NEXT: vmov.16 q1[1], r0
; CHECK-NEXT: vmov.u8 r0, q4[2]
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: vmov.u8 r0, q4[3]
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov.u8 r0, q4[4]
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov.u8 r0, q4[5]
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.u8 r0, q4[6]
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: vmov.u8 r0, q4[7]
; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vcmp.i16 ne, q1, zr
; CHECK-NEXT: vpsel q5, q3, q2
; CHECK-NEXT: vmov.u16 r0, q5[0]
; CHECK-NEXT: vmov.32 q1[0], r0
; CHECK-NEXT: vmov.u16 r0, q5[1]
; CHECK-NEXT: vmov.32 q1[1], r0
; CHECK-NEXT: vmov.u16 r0, q5[2]
; CHECK-NEXT: vmov.32 q1[2], r0
; CHECK-NEXT: vmov.u16 r0, q5[3]
; CHECK-NEXT: vmov.32 q1[3], r0
; CHECK-NEXT: vcmp.i32 ne, q1, zr
; CHECK-NEXT: vmov.i64 q1, #0xff
; CHECK-NEXT: vmrs r0, p0
; CHECK-NEXT: and r1, r0, #1
; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov.32 q6[0], r1
; CHECK-NEXT: vmov.32 q6[1], r1
; CHECK-NEXT: ubfx r1, r0, #4, #1
; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov.32 q6[2], r1
; CHECK-NEXT: vmov.32 q6[3], r1
; CHECK-NEXT: vmov.u8 r1, q0[0]
; CHECK-NEXT: vmov.32 q7[0], r1
; CHECK-NEXT: vmov.u8 r1, q0[1]
; CHECK-NEXT: vmov.32 q7[2], r1
; CHECK-NEXT: vand q7, q7, q1
; CHECK-NEXT: vand q6, q7, q6
; CHECK-NEXT: vmov r1, s27
; CHECK-NEXT: vmov r2, s25
; CHECK-NEXT: vmov r3, s24
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s26
; CHECK-NEXT: add r2, r3
; CHECK-NEXT: ubfx r3, r0, #8, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: ubfx r0, r0, #12, #1
; CHECK-NEXT: vmov.32 q6[0], r3
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmov.32 q6[1], r3
; CHECK-NEXT: vmov.32 q6[2], r0
; CHECK-NEXT: vmov.32 q6[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vmov.32 q7[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[3]
; CHECK-NEXT: vmov.32 q7[2], r0
; CHECK-NEXT: vand q7, q7, q1
; CHECK-NEXT: vand q6, q7, q6
; CHECK-NEXT: vmov r3, s24
; CHECK-NEXT: vmov r0, s25
; CHECK-NEXT: adds r2, r2, r3
; CHECK-NEXT: vmov r3, s27
; CHECK-NEXT: adcs r1, r0
; CHECK-NEXT: vmov r0, s26
; CHECK-NEXT: adds.w r12, r2, r0
; CHECK-NEXT: vmov.u16 r2, q5[4]
; CHECK-NEXT: vmov.32 q6[0], r2
; CHECK-NEXT: vmov.u16 r2, q5[5]
; CHECK-NEXT: vmov.32 q6[1], r2
; CHECK-NEXT: vmov.u16 r2, q5[6]
; CHECK-NEXT: vmov.32 q6[2], r2
; CHECK-NEXT: vmov.u16 r2, q5[7]
; CHECK-NEXT: vmov.32 q6[3], r2
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: vcmp.i32 ne, q6, zr
; CHECK-NEXT: vmrs r2, p0
; CHECK-NEXT: and r3, r2, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q5[0], r3
; CHECK-NEXT: vmov.32 q5[1], r3
; CHECK-NEXT: ubfx r3, r2, #4, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q5[2], r3
; CHECK-NEXT: vmov.32 q5[3], r3
; CHECK-NEXT: vmov.u8 r3, q0[4]
; CHECK-NEXT: vmov.32 q6[0], r3
; CHECK-NEXT: vmov.u8 r3, q0[5]
; CHECK-NEXT: vmov.32 q6[2], r3
; CHECK-NEXT: vand q6, q6, q1
; CHECK-NEXT: vand q5, q6, q5
; CHECK-NEXT: vmov r0, s20
; CHECK-NEXT: vmov r3, s21
; CHECK-NEXT: adds.w r12, r12, r0
; CHECK-NEXT: vmov r0, s22
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: vmov r3, s23
; CHECK-NEXT: adds.w r0, r0, r12
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: ubfx r3, r2, #8, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: ubfx r2, r2, #12, #1
; CHECK-NEXT: vmov.32 q5[0], r3
; CHECK-NEXT: rsbs r2, r2, #0
; CHECK-NEXT: vmov.32 q5[1], r3
; CHECK-NEXT: vmov.32 q5[2], r2
; CHECK-NEXT: vmov.32 q5[3], r2
; CHECK-NEXT: vmov.u8 r2, q0[6]
; CHECK-NEXT: vmov.32 q6[0], r2
; CHECK-NEXT: vmov.u8 r2, q0[7]
; CHECK-NEXT: vmov.32 q6[2], r2
; CHECK-NEXT: vand q6, q6, q1
; CHECK-NEXT: vand q5, q6, q5
; CHECK-NEXT: vmov r3, s20
; CHECK-NEXT: vmov r2, s21
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: vmov r3, s22
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: vmov r2, s23
; CHECK-NEXT: adds.w r12, r0, r3
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: vmov.u8 r2, q4[8]
; CHECK-NEXT: vmov.16 q5[0], r2
; CHECK-NEXT: vmov.u8 r2, q4[9]
; CHECK-NEXT: vmov.16 q5[1], r2
; CHECK-NEXT: vmov.u8 r2, q4[10]
; CHECK-NEXT: vmov.16 q5[2], r2
; CHECK-NEXT: vmov.u8 r2, q4[11]
; CHECK-NEXT: vmov.16 q5[3], r2
; CHECK-NEXT: vmov.u8 r2, q4[12]
; CHECK-NEXT: vmov.16 q5[4], r2
; CHECK-NEXT: vmov.u8 r2, q4[13]
; CHECK-NEXT: vmov.16 q5[5], r2
; CHECK-NEXT: vmov.u8 r2, q4[14]
; CHECK-NEXT: vmov.16 q5[6], r2
; CHECK-NEXT: vmov.u8 r2, q4[15]
; CHECK-NEXT: vmov.16 q5[7], r2
; CHECK-NEXT: vcmp.i16 ne, q5, zr
; CHECK-NEXT: vpsel q2, q3, q2
; CHECK-NEXT: vmov.u16 r2, q2[0]
; CHECK-NEXT: vmov.32 q3[0], r2
; CHECK-NEXT: vmov.u16 r2, q2[1]
; CHECK-NEXT: vmov.32 q3[1], r2
; CHECK-NEXT: vmov.u16 r2, q2[2]
; CHECK-NEXT: vmov.32 q3[2], r2
; CHECK-NEXT: vmov.u16 r2, q2[3]
; CHECK-NEXT: vmov.32 q3[3], r2
; CHECK-NEXT: vcmp.i32 ne, q3, zr
; CHECK-NEXT: vmrs r2, p0
; CHECK-NEXT: and r3, r2, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q3[0], r3
; CHECK-NEXT: vmov.32 q3[1], r3
; CHECK-NEXT: ubfx r3, r2, #4, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q3[2], r3
; CHECK-NEXT: vmov.32 q3[3], r3
; CHECK-NEXT: vmov.u8 r3, q0[8]
; CHECK-NEXT: vmov.32 q4[0], r3
; CHECK-NEXT: vmov.u8 r3, q0[9]
; CHECK-NEXT: vmov.32 q4[2], r3
; CHECK-NEXT: vand q4, q4, q1
; CHECK-NEXT: vand q3, q4, q3
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov r3, s13
; CHECK-NEXT: adds.w r12, r12, r0
; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: vmov r3, s15
; CHECK-NEXT: adds.w r0, r0, r12
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: ubfx r3, r2, #8, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: ubfx r2, r2, #12, #1
; CHECK-NEXT: vmov.32 q3[0], r3
; CHECK-NEXT: rsbs r2, r2, #0
; CHECK-NEXT: vmov.32 q3[1], r3
; CHECK-NEXT: vmov.32 q3[2], r2
; CHECK-NEXT: vmov.32 q3[3], r2
; CHECK-NEXT: vmov.u8 r2, q0[10]
; CHECK-NEXT: vmov.32 q4[0], r2
; CHECK-NEXT: vmov.u8 r2, q0[11]
; CHECK-NEXT: vmov.32 q4[2], r2
; CHECK-NEXT: vand q4, q4, q1
; CHECK-NEXT: vand q3, q4, q3
; CHECK-NEXT: vmov r3, s12
; CHECK-NEXT: vmov r2, s13
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: vmov r3, s14
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: vmov r2, s15
; CHECK-NEXT: adds.w r12, r0, r3
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: vmov.u16 r2, q2[4]
; CHECK-NEXT: vmov.32 q3[0], r2
; CHECK-NEXT: vmov.u16 r2, q2[5]
; CHECK-NEXT: vmov.32 q3[1], r2
; CHECK-NEXT: vmov.u16 r2, q2[6]
; CHECK-NEXT: vmov.32 q3[2], r2
; CHECK-NEXT: vmov.u16 r2, q2[7]
; CHECK-NEXT: vmov.32 q3[3], r2
; CHECK-NEXT: vcmp.i32 ne, q3, zr
; CHECK-NEXT: vmrs r2, p0
; CHECK-NEXT: and r3, r2, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q2[0], r3
; CHECK-NEXT: vmov.32 q2[1], r3
; CHECK-NEXT: ubfx r3, r2, #4, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q2[2], r3
; CHECK-NEXT: vmov.32 q2[3], r3
; CHECK-NEXT: vmov.u8 r3, q0[12]
; CHECK-NEXT: vmov.32 q3[0], r3
; CHECK-NEXT: vmov.u8 r3, q0[13]
; CHECK-NEXT: vmov.32 q3[2], r3
; CHECK-NEXT: vand q3, q3, q1
; CHECK-NEXT: vand q2, q3, q2
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov r3, s9
; CHECK-NEXT: adds.w r12, r12, r0
; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: vmov r3, s11
; CHECK-NEXT: adds.w r0, r0, r12
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: ubfx r3, r2, #8, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: ubfx r2, r2, #12, #1
; CHECK-NEXT: vmov.32 q2[0], r3
; CHECK-NEXT: rsbs r2, r2, #0
; CHECK-NEXT: vmov.32 q2[1], r3
; CHECK-NEXT: vmov.32 q2[2], r2
; CHECK-NEXT: vmov.32 q2[3], r2
; CHECK-NEXT: vmov.u8 r2, q0[14]
; CHECK-NEXT: vmov.32 q3[0], r2
; CHECK-NEXT: vmov.u8 r2, q0[15]
; CHECK-NEXT: vmov.32 q3[2], r2
; CHECK-NEXT: vand q0, q3, q1
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: vmov r2, s3
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <16 x i8> %b, zeroinitializer
%xx = zext <16 x i8> %x to <16 x i64>
%s = select <16 x i1> %c, <16 x i64> %xx, <16 x i64> zeroinitializer
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %s)
ret i64 %z
}
define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_sext(<16 x i8> %x, <16 x i8> %b) {
; CHECK-LABEL: add_v16i8_v16i64_sext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vcmp.i8 eq, q1, zr
; CHECK-NEXT: vmov.i8 q1, #0x0
; CHECK-NEXT: vmov.i8 q2, #0xff
; CHECK-NEXT: vpsel q3, q2, q1
; CHECK-NEXT: vmov.u8 r0, q3[0]
; CHECK-NEXT: vmov.16 q4[0], r0
; CHECK-NEXT: vmov.u8 r0, q3[1]
; CHECK-NEXT: vmov.16 q4[1], r0
; CHECK-NEXT: vmov.u8 r0, q3[2]
; CHECK-NEXT: vmov.16 q4[2], r0
; CHECK-NEXT: vmov.u8 r0, q3[3]
; CHECK-NEXT: vmov.16 q4[3], r0
; CHECK-NEXT: vmov.u8 r0, q3[4]
; CHECK-NEXT: vmov.16 q4[4], r0
; CHECK-NEXT: vmov.u8 r0, q3[5]
; CHECK-NEXT: vmov.16 q4[5], r0
; CHECK-NEXT: vmov.u8 r0, q3[6]
; CHECK-NEXT: vmov.16 q4[6], r0
; CHECK-NEXT: vmov.u8 r0, q3[7]
; CHECK-NEXT: vmov.16 q4[7], r0
; CHECK-NEXT: vcmp.i16 ne, q4, zr
; CHECK-NEXT: vpsel q4, q2, q1
; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: vmov.32 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q4[1]
; CHECK-NEXT: vmov.32 q5[1], r0
; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov.32 q5[2], r0
; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov.32 q5[3], r0
; CHECK-NEXT: vcmp.i32 ne, q5, zr
; CHECK-NEXT: vmrs r0, p0
; CHECK-NEXT: and r1, r0, #1
; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov.32 q5[0], r1
; CHECK-NEXT: vmov.32 q5[1], r1
; CHECK-NEXT: ubfx r1, r0, #4, #1
; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov.32 q5[2], r1
; CHECK-NEXT: vmov.32 q5[3], r1
; CHECK-NEXT: vmov.u8 r1, q0[0]