-
Notifications
You must be signed in to change notification settings - Fork 11.6k
/
riscv_generated_funcs.ll.generated.expected
143 lines (133 loc) · 4.07 KB
/
riscv_generated_funcs.ll.generated.expected
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs
; RUN: llc -enable-machine-outliner -mtriple=riscv32-unknown-linux < %s | FileCheck %s
@x = global i32 0, align 4
define i32 @check_boundaries() #0 {
%1 = alloca i32, align 4
%2 = alloca i32, align 4
%3 = alloca i32, align 4
%4 = alloca i32, align 4
%5 = alloca i32, align 4
store i32 0, i32* %1, align 4
store i32 0, i32* %2, align 4
%6 = load i32, i32* %2, align 4
%7 = icmp ne i32 %6, 0
br i1 %7, label %9, label %8
store i32 1, i32* %2, align 4
store i32 2, i32* %3, align 4
store i32 3, i32* %4, align 4
store i32 4, i32* %5, align 4
br label %10
store i32 1, i32* %4, align 4
br label %10
%11 = load i32, i32* %2, align 4
%12 = icmp ne i32 %11, 0
br i1 %12, label %14, label %13
store i32 1, i32* %2, align 4
store i32 2, i32* %3, align 4
store i32 3, i32* %4, align 4
store i32 4, i32* %5, align 4
br label %15
store i32 1, i32* %4, align 4
br label %15
ret i32 0
}
define i32 @main() #0 {
%1 = alloca i32, align 4
%2 = alloca i32, align 4
%3 = alloca i32, align 4
%4 = alloca i32, align 4
%5 = alloca i32, align 4
store i32 0, i32* %1, align 4
store i32 0, i32* @x, align 4
store i32 1, i32* %2, align 4
store i32 2, i32* %3, align 4
store i32 3, i32* %4, align 4
store i32 4, i32* %5, align 4
store i32 1, i32* @x, align 4
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
store i32 1, i32* %2, align 4
store i32 2, i32* %3, align 4
store i32 3, i32* %4, align 4
store i32 4, i32* %5, align 4
ret i32 0
}
attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
; CHECK-LABEL: check_boundaries:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: sw ra, 28(sp)
; CHECK-NEXT: sw s0, 24(sp)
; CHECK-NEXT: .cfi_offset ra, -4
; CHECK-NEXT: .cfi_offset s0, -8
; CHECK-NEXT: addi s0, sp, 32
; CHECK-NEXT: .cfi_def_cfa s0, 0
; CHECK-NEXT: sw zero, -12(s0)
; CHECK-NEXT: sw zero, -16(s0)
; CHECK-NEXT: addi a0, zero, 1
; CHECK-NEXT: beqz zero, .LBB0_3
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: sw a0, -24(s0)
; CHECK-NEXT: lw a0, -16(s0)
; CHECK-NEXT: beqz a0, .LBB0_4
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: addi a0, zero, 1
; CHECK-NEXT: sw a0, -24(s0)
; CHECK-NEXT: j .LBB0_5
; CHECK-NEXT: .LBB0_3:
; CHECK-NEXT: call t0, OUTLINED_FUNCTION_0
; CHECK-NEXT: lw a0, -16(s0)
; CHECK-NEXT: bnez a0, .LBB0_2
; CHECK-NEXT: .LBB0_4:
; CHECK-NEXT: addi a0, zero, 1
; CHECK-NEXT: call t0, OUTLINED_FUNCTION_0
; CHECK-NEXT: .LBB0_5:
; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: lw s0, 24(sp)
; CHECK-NEXT: lw ra, 28(sp)
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
;
; CHECK-LABEL: main:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: sw ra, 28(sp)
; CHECK-NEXT: sw s0, 24(sp)
; CHECK-NEXT: .cfi_offset ra, -4
; CHECK-NEXT: .cfi_offset s0, -8
; CHECK-NEXT: addi s0, sp, 32
; CHECK-NEXT: .cfi_def_cfa s0, 0
; CHECK-NEXT: sw zero, -12(s0)
; CHECK-NEXT: lui a0, %hi(x)
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: sw a1, -16(s0)
; CHECK-NEXT: addi a2, zero, 2
; CHECK-NEXT: sw a2, -20(s0)
; CHECK-NEXT: addi a3, zero, 3
; CHECK-NEXT: sw a3, -24(s0)
; CHECK-NEXT: addi a4, zero, 4
; CHECK-NEXT: sw a4, -28(s0)
; CHECK-NEXT: sw a1, %lo(x)(a0)
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: sw a1, -16(s0)
; CHECK-NEXT: sw a2, -20(s0)
; CHECK-NEXT: sw a3, -24(s0)
; CHECK-NEXT: sw a4, -28(s0)
; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: lw s0, 24(sp)
; CHECK-NEXT: lw ra, 28(sp)
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
;
; CHECK-LABEL: OUTLINED_FUNCTION_0:
; CHECK: # %bb.0:
; CHECK-NEXT: sw a0, -16(s0)
; CHECK-NEXT: addi a0, zero, 2
; CHECK-NEXT: sw a0, -20(s0)
; CHECK-NEXT: addi a0, zero, 3
; CHECK-NEXT: sw a0, -24(s0)
; CHECK-NEXT: addi a0, zero, 4
; CHECK-NEXT: sw a0, -28(s0)
; CHECK-NEXT: jr t0