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vlsseg-rv32.ll
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vlsseg-rv32.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
; RUN: -verify-machineinstrs < %s | FileCheck %s
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(i16*, i32, i32)
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i32, <vscale x 16 x i1>, i32, i32)
define <vscale x 16 x i16> @test_vlsseg2_nxv16i16(i16* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg2_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
ret <vscale x 16 x i16> %1
}
define <vscale x 16 x i16> @test_vlsseg2_mask_nxv16i16(i16* %base, i32 %offset, i32 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlsseg2_mask_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1
; CHECK-NEXT: vmv4r.v v8, v4
; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
ret <vscale x 16 x i16> %3
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.nxv1i8(i8*, i32, i32)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)
define <vscale x 1 x i8> @test_vlsseg2_nxv1i8(i8* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg2_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.nxv1i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlsseg2_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
; CHECK-LABEL: test_vlsseg2_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.nxv1i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
ret <vscale x 1 x i8> %3
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.nxv1i8(i8*, i32, i32)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)
define <vscale x 1 x i8> @test_vlsseg3_nxv1i8(i8* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg3_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.nxv1i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlsseg3_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
; CHECK-LABEL: test_vlsseg3_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.nxv1i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
ret <vscale x 1 x i8> %3
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.nxv1i8(i8*, i32, i32)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)
define <vscale x 1 x i8> @test_vlsseg4_nxv1i8(i8* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg4_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.nxv1i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlsseg4_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
; CHECK-LABEL: test_vlsseg4_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.nxv1i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
ret <vscale x 1 x i8> %3
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.nxv1i8(i8*, i32, i32)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)
define <vscale x 1 x i8> @test_vlsseg5_nxv1i8(i8* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg5_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.nxv1i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlsseg5_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
; CHECK-LABEL: test_vlsseg5_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.nxv1i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
ret <vscale x 1 x i8> %3
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.nxv1i8(i8*, i32, i32)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)
define <vscale x 1 x i8> @test_vlsseg6_nxv1i8(i8* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg6_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.nxv1i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlsseg6_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
; CHECK-LABEL: test_vlsseg6_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.nxv1i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
ret <vscale x 1 x i8> %3
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.nxv1i8(i8*, i32, i32)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)
define <vscale x 1 x i8> @test_vlsseg7_nxv1i8(i8* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg7_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.nxv1i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlsseg7_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
; CHECK-LABEL: test_vlsseg7_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.nxv1i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
ret <vscale x 1 x i8> %3
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.nxv1i8(i8*, i32, i32)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)
define <vscale x 1 x i8> @test_vlsseg8_nxv1i8(i8* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.nxv1i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlsseg8_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
; CHECK-LABEL: test_vlsseg8_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.nxv1i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
ret <vscale x 1 x i8> %3
}
declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.nxv16i8(i8*, i32, i32)
declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, <vscale x 16 x i1>, i32, i32)
define <vscale x 16 x i8> @test_vlsseg2_nxv16i8(i8* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg2_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.nxv16i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
ret <vscale x 16 x i8> %1
}
define <vscale x 16 x i8> @test_vlsseg2_mask_nxv16i8(i8* %base, i32 %offset, i32 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlsseg2_mask_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1
; CHECK-NEXT: vmv2r.v v8, v6
; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.nxv16i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
ret <vscale x 16 x i8> %3
}
declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.nxv16i8(i8*, i32, i32)
declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, <vscale x 16 x i1>, i32, i32)
define <vscale x 16 x i8> @test_vlsseg3_nxv16i8(i8* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg3_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.nxv16i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
ret <vscale x 16 x i8> %1
}
define <vscale x 16 x i8> @test_vlsseg3_mask_nxv16i8(i8* %base, i32 %offset, i32 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlsseg3_mask_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1
; CHECK-NEXT: vmv2r.v v8, v6
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.nxv16i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
ret <vscale x 16 x i8> %3
}
declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.nxv16i8(i8*, i32, i32)
declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, <vscale x 16 x i1>, i32, i32)
define <vscale x 16 x i8> @test_vlsseg4_nxv16i8(i8* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg4_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.nxv16i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
ret <vscale x 16 x i8> %1
}
define <vscale x 16 x i8> @test_vlsseg4_mask_nxv16i8(i8* %base, i32 %offset, i32 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlsseg4_mask_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1
; CHECK-NEXT: vmv2r.v v8, v6
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vmv2r.v v12, v6
; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.nxv16i8(i8* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
ret <vscale x 16 x i8> %3
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.nxv2i32(i32*, i32, i32)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)
define <vscale x 2 x i32> @test_vlsseg2_nxv2i32(i32* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg2_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.nxv2i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlsseg2_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
; CHECK-LABEL: test_vlsseg2_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.nxv2i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
ret <vscale x 2 x i32> %3
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.nxv2i32(i32*, i32, i32)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)
define <vscale x 2 x i32> @test_vlsseg3_nxv2i32(i32* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg3_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.nxv2i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlsseg3_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
; CHECK-LABEL: test_vlsseg3_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.nxv2i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
ret <vscale x 2 x i32> %3
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.nxv2i32(i32*, i32, i32)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)
define <vscale x 2 x i32> @test_vlsseg4_nxv2i32(i32* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg4_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.nxv2i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlsseg4_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
; CHECK-LABEL: test_vlsseg4_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.nxv2i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
ret <vscale x 2 x i32> %3
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.nxv2i32(i32*, i32, i32)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)
define <vscale x 2 x i32> @test_vlsseg5_nxv2i32(i32* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg5_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.nxv2i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlsseg5_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
; CHECK-LABEL: test_vlsseg5_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.nxv2i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
ret <vscale x 2 x i32> %3
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.nxv2i32(i32*, i32, i32)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)
define <vscale x 2 x i32> @test_vlsseg6_nxv2i32(i32* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg6_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.nxv2i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlsseg6_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
; CHECK-LABEL: test_vlsseg6_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.nxv2i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
ret <vscale x 2 x i32> %3
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.nxv2i32(i32*, i32, i32)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)
define <vscale x 2 x i32> @test_vlsseg7_nxv2i32(i32* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg7_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.nxv2i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlsseg7_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
; CHECK-LABEL: test_vlsseg7_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.nxv2i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
ret <vscale x 2 x i32> %3
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.nxv2i32(i32*, i32, i32)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)
define <vscale x 2 x i32> @test_vlsseg8_nxv2i32(i32* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.nxv2i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlsseg8_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
; CHECK-LABEL: test_vlsseg8_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.nxv2i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
ret <vscale x 2 x i32> %3
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.nxv4i16(i16*, i32, i32)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)
define <vscale x 4 x i16> @test_vlsseg2_nxv4i16(i16* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg2_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.nxv4i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlsseg2_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
; CHECK-LABEL: test_vlsseg2_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.nxv4i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
ret <vscale x 4 x i16> %3
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.nxv4i16(i16*, i32, i32)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)
define <vscale x 4 x i16> @test_vlsseg3_nxv4i16(i16* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg3_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.nxv4i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlsseg3_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
; CHECK-LABEL: test_vlsseg3_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.nxv4i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
ret <vscale x 4 x i16> %3
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.nxv4i16(i16*, i32, i32)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)
define <vscale x 4 x i16> @test_vlsseg4_nxv4i16(i16* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg4_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.nxv4i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlsseg4_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
; CHECK-LABEL: test_vlsseg4_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.nxv4i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
ret <vscale x 4 x i16> %3
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.nxv4i16(i16*, i32, i32)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)
define <vscale x 4 x i16> @test_vlsseg5_nxv4i16(i16* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg5_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.nxv4i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlsseg5_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
; CHECK-LABEL: test_vlsseg5_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.nxv4i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
ret <vscale x 4 x i16> %3
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.nxv4i16(i16*, i32, i32)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)
define <vscale x 4 x i16> @test_vlsseg6_nxv4i16(i16* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg6_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.nxv4i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlsseg6_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
; CHECK-LABEL: test_vlsseg6_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.nxv4i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
ret <vscale x 4 x i16> %3
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.nxv4i16(i16*, i32, i32)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)
define <vscale x 4 x i16> @test_vlsseg7_nxv4i16(i16* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg7_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.nxv4i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlsseg7_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
; CHECK-LABEL: test_vlsseg7_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.nxv4i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
ret <vscale x 4 x i16> %3
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.nxv4i16(i16*, i32, i32)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)
define <vscale x 4 x i16> @test_vlsseg8_nxv4i16(i16* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.nxv4i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlsseg8_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
; CHECK-LABEL: test_vlsseg8_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.nxv4i16(i16* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
ret <vscale x 4 x i16> %3
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(i32*, i32, i32)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)
define <vscale x 1 x i32> @test_vlsseg2_nxv1i32(i32* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg2_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlsseg2_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
; CHECK-LABEL: test_vlsseg2_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
ret <vscale x 1 x i32> %3
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(i32*, i32, i32)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)
define <vscale x 1 x i32> @test_vlsseg3_nxv1i32(i32* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg3_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlsseg3_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
; CHECK-LABEL: test_vlsseg3_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
ret <vscale x 1 x i32> %3
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(i32*, i32, i32)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)
define <vscale x 1 x i32> @test_vlsseg4_nxv1i32(i32* %base, i32 %offset, i32 %vl) {
; CHECK-LABEL: test_vlsseg4_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlsseg4_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
; CHECK-LABEL: test_vlsseg4_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(i32* %base, i32 %offset, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
ret <vscale x 1 x i32> %3
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(i32*, i32, i32)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)