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thumb-select-logical-ops.mir
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thumb-select-logical-ops.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
define void @test_and_regs() { ret void }
define void @test_and_imm() { ret void }
define void @test_bfc() { ret void }
define void @test_no_bfc_bad_mask() { ret void }
define void @test_mvn() { ret void }
define void @test_bic() { ret void }
define void @test_orn() { ret void }
...
---
name: test_and_regs
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_and_regs
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2ANDrr:%[0-9]+]]:rgpr = t2ANDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s32) = G_AND %0, %1
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_and_imm
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_and_imm
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
%2(s32) = G_AND %0, %1
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_bfc
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_bfc
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2BFC:%[0-9]+]]:rgpr = t2BFC [[COPY]], -65529, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2BFC]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = G_CONSTANT i32 -65529 ; 0xFFFF0007
%2(s32) = G_AND %0, %1
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_no_bfc_bad_mask
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_no_bfc_bad_mask
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
%2(s32) = G_AND %0, %1
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_mvn
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_mvn
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2MVNr:%[0-9]+]]:rgpr = t2MVNr [[COPY]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2MVNr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = G_CONSTANT i32 -1
%2(s32) = G_XOR %0, %1
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_bic
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_bic
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2BICrr:%[0-9]+]]:rgpr = t2BICrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2BICrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2
%4(s32) = G_AND %0, %3
$r0 = COPY %4(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_orn
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_orn
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2ORNrr:%[0-9]+]]:rgpr = t2ORNrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ORNrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2
%4(s32) = G_OR %0, %3
$r0 = COPY %4(s32)
BX_RET 14, $noreg, implicit $r0
...