-
Notifications
You must be signed in to change notification settings - Fork 11.6k
/
partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll
273 lines (247 loc) · 11.2 KB
/
partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
; If we have some pattern that leaves only some low bits set, and then performs
; left-shift of those bits, we can combine those two shifts into a shift+mask.
; There are many variants to this pattern:
; a) (trunc (x & ((1 << maskNbits) - 1))) << shiftNbits
; simplify to:
; ((trunc(x)) << shiftNbits) & (~(-1 << (maskNbits+shiftNbits)))
; Simple tests.
declare void @use32(i32)
declare void @use64(i64)
define i32 @t0_basic(i64 %x, i32 %nbits) {
; CHECK-LABEL: @t0_basic(
; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], -1
; CHECK-NEXT: [[T1:%.*]] = zext i32 [[T0]] to i64
; CHECK-NEXT: [[T2:%.*]] = shl i64 1, [[T1]]
; CHECK-NEXT: [[T3:%.*]] = add i64 [[T2]], -1
; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use64(i64 [[T1]])
; CHECK-NEXT: call void @use64(i64 [[T2]])
; CHECK-NEXT: call void @use64(i64 [[T3]])
; CHECK-NEXT: call void @use32(i32 [[T4]])
; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], [[T4]]
; CHECK-NEXT: [[T7:%.*]] = and i32 [[TMP2]], 2147483647
; CHECK-NEXT: ret i32 [[T7]]
;
%t0 = add i32 %nbits, -1
%t1 = zext i32 %t0 to i64
%t2 = shl i64 1, %t1 ; shifting by nbits-1
%t3 = add i64 %t2, -1
%t4 = sub i32 32, %nbits
call void @use32(i32 %t0)
call void @use64(i64 %t1)
call void @use64(i64 %t2)
call void @use64(i64 %t3)
call void @use32(i32 %t4)
%t5 = and i64 %t3, %x
%t6 = trunc i64 %t5 to i32
%t7 = shl i32 %t6, %t4
ret i32 %t7
}
; Vectors
declare void @use8xi32(<8 x i32>)
declare void @use8xi64(<8 x i64>)
define <8 x i32> @t1_vec_splat(<8 x i64> %x, <8 x i32> %nbits) {
; CHECK-LABEL: @t1_vec_splat(
; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: [[T1:%.*]] = zext <8 x i32> [[T0]] to <8 x i64>
; CHECK-NEXT: [[T2:%.*]] = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>, [[T1]]
; CHECK-NEXT: [[T3:%.*]] = add <8 x i64> [[T2]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, [[NBITS]]
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T1]])
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T2]])
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T3]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X:%.*]] to <8 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T4]]
; CHECK-NEXT: [[T7:%.*]] = and <8 x i32> [[TMP2]], <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
; CHECK-NEXT: ret <8 x i32> [[T7]]
;
%t0 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
%t1 = zext <8 x i32> %t0 to <8 x i64>
%t2 = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>, %t1 ; shifting by nbits-1
%t3 = add <8 x i64> %t2, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
%t4 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, %nbits
call void @use8xi32(<8 x i32> %t0)
call void @use8xi64(<8 x i64> %t1)
call void @use8xi64(<8 x i64> %t2)
call void @use8xi64(<8 x i64> %t3)
call void @use8xi32(<8 x i32> %t4)
%t5 = and <8 x i64> %t3, %x
%t6 = trunc <8 x i64> %t5 to <8 x i32>
%t7 = shl <8 x i32> %t6, %t4
ret <8 x i32> %t7
}
define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) {
; CHECK-LABEL: @t2_vec_splat_undef(
; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
; CHECK-NEXT: [[T1:%.*]] = zext <8 x i32> [[T0]] to <8 x i64>
; CHECK-NEXT: [[T2:%.*]] = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 undef, i64 1>, [[T1]]
; CHECK-NEXT: [[T3:%.*]] = add <8 x i64> [[T2]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 undef, i64 -1>
; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, [[NBITS]]
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T1]])
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T2]])
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T3]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X:%.*]] to <8 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T4]]
; CHECK-NEXT: [[T7:%.*]] = and <8 x i32> [[TMP2]], <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 undef, i32 2147483647>
; CHECK-NEXT: ret <8 x i32> [[T7]]
;
%t0 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
%t1 = zext <8 x i32> %t0 to <8 x i64>
%t2 = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 undef, i64 1>, %t1 ; shifting by nbits-1
%t3 = add <8 x i64> %t2, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 undef, i64 -1>
%t4 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, %nbits
call void @use8xi32(<8 x i32> %t0)
call void @use8xi64(<8 x i64> %t1)
call void @use8xi64(<8 x i64> %t2)
call void @use8xi64(<8 x i64> %t3)
call void @use8xi32(<8 x i32> %t4)
%t5 = and <8 x i64> %t3, %x
%t6 = trunc <8 x i64> %t5 to <8 x i32>
%t7 = shl <8 x i32> %t6, %t4
ret <8 x i32> %t7
}
define <8 x i32> @t3_vec_nonsplat(<8 x i64> %x, <8 x i32> %nbits) {
; CHECK-LABEL: @t3_vec_nonsplat(
; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], <i32 -33, i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32>
; CHECK-NEXT: [[T1:%.*]] = zext <8 x i32> [[T0]] to <8 x i64>
; CHECK-NEXT: [[T2:%.*]] = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>, [[T1]]
; CHECK-NEXT: [[T3:%.*]] = add <8 x i64> [[T2]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, [[NBITS]]
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T1]])
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T2]])
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T3]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X:%.*]] to <8 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T4]]
; CHECK-NEXT: [[T7:%.*]] = and <8 x i32> [[TMP2]], <i32 undef, i32 0, i32 1, i32 2147483647, i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: ret <8 x i32> [[T7]]
;
%t0 = add <8 x i32> %nbits, <i32 -33, i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32>
%t1 = zext <8 x i32> %t0 to <8 x i64>
%t2 = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>, %t1 ; shifting by nbits-1
%t3 = add <8 x i64> %t2, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
%t4 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, %nbits
call void @use8xi32(<8 x i32> %t0)
call void @use8xi64(<8 x i64> %t1)
call void @use8xi64(<8 x i64> %t2)
call void @use8xi64(<8 x i64> %t3)
call void @use8xi32(<8 x i32> %t4)
%t5 = and <8 x i64> %t3, %x
%t6 = trunc <8 x i64> %t5 to <8 x i32>
%t7 = shl <8 x i32> %t6, %t4
ret <8 x i32> %t7
}
; Extra uses
define i32 @n4_extrause0(i64 %x, i32 %nbits) {
; CHECK-LABEL: @n4_extrause0(
; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], -1
; CHECK-NEXT: [[T1:%.*]] = zext i32 [[T0]] to i64
; CHECK-NEXT: [[T2:%.*]] = shl i64 1, [[T1]]
; CHECK-NEXT: [[T3:%.*]] = add i64 [[T2]], -1
; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use64(i64 [[T1]])
; CHECK-NEXT: call void @use64(i64 [[T2]])
; CHECK-NEXT: call void @use64(i64 [[T3]])
; CHECK-NEXT: call void @use32(i32 [[T4]])
; CHECK-NEXT: [[T5:%.*]] = and i64 [[T3]], [[X:%.*]]
; CHECK-NEXT: call void @use64(i64 [[T5]])
; CHECK-NEXT: [[T6:%.*]] = trunc i64 [[T5]] to i32
; CHECK-NEXT: [[T7:%.*]] = shl i32 [[T6]], [[T4]]
; CHECK-NEXT: ret i32 [[T7]]
;
%t0 = add i32 %nbits, -1
%t1 = zext i32 %t0 to i64
%t2 = shl i64 1, %t1 ; shifting by nbits-1
%t3 = add i64 %t2, -1
%t4 = sub i32 32, %nbits
call void @use32(i32 %t0)
call void @use64(i64 %t1)
call void @use64(i64 %t2)
call void @use64(i64 %t3)
call void @use32(i32 %t4)
%t5 = and i64 %t3, %x
call void @use64(i64 %t5)
%t6 = trunc i64 %t5 to i32
%t7 = shl i32 %t6, %t4
ret i32 %t7
}
define i32 @n5_extrause1(i64 %x, i32 %nbits) {
; CHECK-LABEL: @n5_extrause1(
; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], -1
; CHECK-NEXT: [[T1:%.*]] = zext i32 [[T0]] to i64
; CHECK-NEXT: [[T2:%.*]] = shl i64 1, [[T1]]
; CHECK-NEXT: [[T3:%.*]] = add i64 [[T2]], -1
; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use64(i64 [[T1]])
; CHECK-NEXT: call void @use64(i64 [[T2]])
; CHECK-NEXT: call void @use64(i64 [[T3]])
; CHECK-NEXT: call void @use32(i32 [[T4]])
; CHECK-NEXT: [[T5:%.*]] = and i64 [[T3]], [[X:%.*]]
; CHECK-NEXT: [[T6:%.*]] = trunc i64 [[T5]] to i32
; CHECK-NEXT: call void @use32(i32 [[T6]])
; CHECK-NEXT: [[T7:%.*]] = shl i32 [[T6]], [[T4]]
; CHECK-NEXT: ret i32 [[T7]]
;
%t0 = add i32 %nbits, -1
%t1 = zext i32 %t0 to i64
%t2 = shl i64 1, %t1 ; shifting by nbits-1
%t3 = add i64 %t2, -1
%t4 = sub i32 32, %nbits
call void @use32(i32 %t0)
call void @use64(i64 %t1)
call void @use64(i64 %t2)
call void @use64(i64 %t3)
call void @use32(i32 %t4)
%t5 = and i64 %t3, %x
%t6 = trunc i64 %t5 to i32
call void @use32(i32 %t6)
%t7 = shl i32 %t6, %t4
ret i32 %t7
}
define i32 @n6_extrause2(i64 %x, i32 %nbits) {
; CHECK-LABEL: @n6_extrause2(
; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], -1
; CHECK-NEXT: [[T1:%.*]] = zext i32 [[T0]] to i64
; CHECK-NEXT: [[T2:%.*]] = shl i64 1, [[T1]]
; CHECK-NEXT: [[T3:%.*]] = add i64 [[T2]], -1
; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use64(i64 [[T1]])
; CHECK-NEXT: call void @use64(i64 [[T2]])
; CHECK-NEXT: call void @use64(i64 [[T3]])
; CHECK-NEXT: call void @use32(i32 [[T4]])
; CHECK-NEXT: [[T5:%.*]] = and i64 [[T3]], [[X:%.*]]
; CHECK-NEXT: call void @use64(i64 [[T5]])
; CHECK-NEXT: [[T6:%.*]] = trunc i64 [[T5]] to i32
; CHECK-NEXT: call void @use32(i32 [[T6]])
; CHECK-NEXT: [[T7:%.*]] = shl i32 [[T6]], [[T4]]
; CHECK-NEXT: ret i32 [[T7]]
;
%t0 = add i32 %nbits, -1
%t1 = zext i32 %t0 to i64
%t2 = shl i64 1, %t1 ; shifting by nbits-1
%t3 = add i64 %t2, -1
%t4 = sub i32 32, %nbits
call void @use32(i32 %t0)
call void @use64(i64 %t1)
call void @use64(i64 %t2)
call void @use64(i64 %t3)
call void @use32(i32 %t4)
%t5 = and i64 %t3, %x
call void @use64(i64 %t5)
%t6 = trunc i64 %t5 to i32
call void @use32(i32 %t6)
%t7 = shl i32 %t6, %t4
ret i32 %t7
}