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Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to i…
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…mprove usage of those instructions."

I thought this might help with another optimization I was
thinking about, but I don't think it will. So it just wastes
compile time calling computeKnownBits for no benefit.

This reverts commit 81b2f95.
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@topperc
topperc committed Jun 27, 2021
1 parent f00941e commit 010f0f0
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Showing 14 changed files with 551 additions and 551 deletions.
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Expand Up @@ -1262,11 +1262,11 @@ def : Pat<(sext_inreg (sub GPR:$rs1, GPR:$rs2), i32),
(SUBW GPR:$rs1, GPR:$rs2)>;
def : Pat<(sext_inreg (shl GPR:$rs1, uimm5:$shamt), i32),
(SLLIW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(i64 (srl (zexti32 (i64 GPR:$rs1)), uimm5:$shamt)),
def : Pat<(i64 (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt)),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(i64 (srl (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt)),
(SRLIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>;
def : Pat<(i64 (sra (sexti32 (i64 GPR:$rs1)), uimm5:$shamt)),
def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
(SRAIW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(i64 (sra (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt)),
(SRAIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>;
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/alu8.ll
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Expand Up @@ -124,7 +124,7 @@ define i8 @srli(i8 %a) nounwind {
; RV64I-LABEL: srli:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 192
; RV64I-NEXT: srliw a0, a0, 6
; RV64I-NEXT: srli a0, a0, 6
; RV64I-NEXT: ret
%1 = lshr i8 %a, 6
ret i8 %1
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
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Expand Up @@ -499,9 +499,9 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/copysign-casts.ll
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Expand Up @@ -357,7 +357,7 @@ define half @fold_demote_h_s(half %a, float %b) nounwind {
; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: slli a2, a2, 31
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srliw a1, a1, 16
; RV64I-NEXT: srli a1, a1, 16
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/div.ll
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Expand Up @@ -276,7 +276,7 @@ define i8 @udiv8_constant(i8 %a) nounwind {
; RV64IM-NEXT: andi a0, a0, 255
; RV64IM-NEXT: addi a1, zero, 205
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srliw a0, a0, 10
; RV64IM-NEXT: srli a0, a0, 10
; RV64IM-NEXT: ret
%1 = udiv i8 %a, 5
ret i8 %1
Expand All @@ -298,13 +298,13 @@ define i8 @udiv8_pow2(i8 %a) nounwind {
; RV64I-LABEL: udiv8_pow2:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 248
; RV64I-NEXT: srliw a0, a0, 3
; RV64I-NEXT: srli a0, a0, 3
; RV64I-NEXT: ret
;
; RV64IM-LABEL: udiv8_pow2:
; RV64IM: # %bb.0:
; RV64IM-NEXT: andi a0, a0, 248
; RV64IM-NEXT: srliw a0, a0, 3
; RV64IM-NEXT: srli a0, a0, 3
; RV64IM-NEXT: ret
%1 = udiv i8 %a, 8
ret i8 %1
Expand Down Expand Up @@ -404,7 +404,7 @@ define i16 @udiv16_constant(i16 %a) nounwind {
; RV64IM-NEXT: lui a1, 13
; RV64IM-NEXT: addiw a1, a1, -819
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srliw a0, a0, 18
; RV64IM-NEXT: srli a0, a0, 18
; RV64IM-NEXT: ret
%1 = udiv i16 %a, 5
ret i16 %1
Expand Down Expand Up @@ -786,7 +786,7 @@ define i8 @sdiv8_constant(i8 %a) nounwind {
; RV64IM-NEXT: srai a0, a0, 56
; RV64IM-NEXT: addi a1, zero, 103
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: sraiw a1, a0, 9
; RV64IM-NEXT: srai a1, a0, 9
; RV64IM-NEXT: srli a0, a0, 15
; RV64IM-NEXT: andi a0, a0, 1
; RV64IM-NEXT: add a0, a1, a0
Expand Down Expand Up @@ -935,7 +935,7 @@ define i16 @sdiv16_constant(i16 %a) nounwind {
; RV64IM-NEXT: lui a1, 6
; RV64IM-NEXT: addiw a1, a1, 1639
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: sraiw a1, a0, 17
; RV64IM-NEXT: srai a1, a0, 17
; RV64IM-NEXT: srli a0, a0, 31
; RV64IM-NEXT: andi a0, a0, 1
; RV64IM-NEXT: add a0, a1, a0
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10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
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Expand Up @@ -1529,7 +1529,7 @@ define i32 @aext_srliw_sext(i32 signext %a) nounwind {
define i32 @aext_srliw_zext(i32 zeroext %a) nounwind {
; RV64I-LABEL: aext_srliw_zext:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a0, a0, 3
; RV64I-NEXT: srli a0, a0, 3
; RV64I-NEXT: ret
%1 = lshr i32 %a, 3
ret i32 %1
Expand All @@ -1556,7 +1556,7 @@ define signext i32 @sext_srliw_sext(i32 signext %a) nounwind {
define signext i32 @sext_srliw_zext(i32 zeroext %a) nounwind {
; RV64I-LABEL: sext_srliw_zext:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a0, a0, 6
; RV64I-NEXT: srli a0, a0, 6
; RV64I-NEXT: ret
%1 = lshr i32 %a, 6
ret i32 %1
Expand All @@ -1583,7 +1583,7 @@ define zeroext i32 @zext_srliw_sext(i32 signext %a) nounwind {
define zeroext i32 @zext_srliw_zext(i32 zeroext %a) nounwind {
; RV64I-LABEL: zext_srliw_zext:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a0, a0, 9
; RV64I-NEXT: srli a0, a0, 9
; RV64I-NEXT: ret
%1 = lshr i32 %a, 9
ret i32 %1
Expand All @@ -1603,7 +1603,7 @@ define i32 @aext_sraiw_aext(i32 %a) nounwind {
define i32 @aext_sraiw_sext(i32 signext %a) nounwind {
; RV64I-LABEL: aext_sraiw_sext:
; RV64I: # %bb.0:
; RV64I-NEXT: sraiw a0, a0, 2
; RV64I-NEXT: srai a0, a0, 2
; RV64I-NEXT: ret
%1 = ashr i32 %a, 2
ret i32 %1
Expand All @@ -1630,7 +1630,7 @@ define signext i32 @sext_sraiw_aext(i32 %a) nounwind {
define signext i32 @sext_sraiw_sext(i32 signext %a) nounwind {
; RV64I-LABEL: sext_sraiw_sext:
; RV64I: # %bb.0:
; RV64I-NEXT: sraiw a0, a0, 5
; RV64I-NEXT: srai a0, a0, 5
; RV64I-NEXT: ret
%1 = ashr i32 %a, 5
ret i32 %1
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22 changes: 11 additions & 11 deletions llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
View file
Expand Up @@ -614,25 +614,25 @@ define i8 @srli_i8(i8 %a) nounwind {
; RV64I-LABEL: srli_i8:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 192
; RV64I-NEXT: srliw a0, a0, 6
; RV64I-NEXT: srli a0, a0, 6
; RV64I-NEXT: ret
;
; RV64IB-LABEL: srli_i8:
; RV64IB: # %bb.0:
; RV64IB-NEXT: andi a0, a0, 192
; RV64IB-NEXT: srliw a0, a0, 6
; RV64IB-NEXT: srli a0, a0, 6
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: srli_i8:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: andi a0, a0, 192
; RV64IBB-NEXT: srliw a0, a0, 6
; RV64IBB-NEXT: srli a0, a0, 6
; RV64IBB-NEXT: ret
;
; RV64IBP-LABEL: srli_i8:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: andi a0, a0, 192
; RV64IBP-NEXT: srliw a0, a0, 6
; RV64IBP-NEXT: srli a0, a0, 6
; RV64IBP-NEXT: ret
%1 = lshr i8 %a, 6
ret i8 %1
Expand All @@ -648,13 +648,13 @@ define i8 @srai_i8(i8 %a) nounwind {
; RV64IB-LABEL: srai_i8:
; RV64IB: # %bb.0:
; RV64IB-NEXT: sext.b a0, a0
; RV64IB-NEXT: sraiw a0, a0, 5
; RV64IB-NEXT: srai a0, a0, 5
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: srai_i8:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: sext.b a0, a0
; RV64IBB-NEXT: sraiw a0, a0, 5
; RV64IBB-NEXT: srai a0, a0, 5
; RV64IBB-NEXT: ret
;
; RV64IBP-LABEL: srai_i8:
Expand All @@ -676,19 +676,19 @@ define i16 @srli_i16(i16 %a) nounwind {
; RV64IB-LABEL: srli_i16:
; RV64IB: # %bb.0:
; RV64IB-NEXT: zext.h a0, a0
; RV64IB-NEXT: srliw a0, a0, 6
; RV64IB-NEXT: srli a0, a0, 6
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: srli_i16:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: zext.h a0, a0
; RV64IBB-NEXT: srliw a0, a0, 6
; RV64IBB-NEXT: srli a0, a0, 6
; RV64IBB-NEXT: ret
;
; RV64IBP-LABEL: srli_i16:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: zext.h a0, a0
; RV64IBP-NEXT: srliw a0, a0, 6
; RV64IBP-NEXT: srli a0, a0, 6
; RV64IBP-NEXT: ret
%1 = lshr i16 %a, 6
ret i16 %1
Expand All @@ -704,13 +704,13 @@ define i16 @srai_i16(i16 %a) nounwind {
; RV64IB-LABEL: srai_i16:
; RV64IB: # %bb.0:
; RV64IB-NEXT: sext.h a0, a0
; RV64IB-NEXT: sraiw a0, a0, 9
; RV64IB-NEXT: srai a0, a0, 9
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: srai_i16:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: sext.h a0, a0
; RV64IBB-NEXT: sraiw a0, a0, 9
; RV64IBB-NEXT: srai a0, a0, 9
; RV64IBB-NEXT: ret
;
; RV64IBP-LABEL: srai_i16:
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/rv64zbb.ll
View file
Expand Up @@ -19,9 +19,9 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
Expand Down Expand Up @@ -105,9 +105,9 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
Expand Down Expand Up @@ -202,9 +202,9 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
Expand Down Expand Up @@ -295,9 +295,9 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: srliw a1, s0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
Expand Down Expand Up @@ -395,11 +395,11 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-NEXT: srliw a0, a0, 1
; RV64I-NEXT: beqz a0, .LBB4_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
Expand Down Expand Up @@ -1016,7 +1016,7 @@ define signext i32 @ctpop_i32_load(i32* %p) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lwu a0, 0(a0)
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
Expand Down

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