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Revert "[M68k][GloballSel] Formal arguments lowering in IRTranslator"
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This reverts commit 8f43407 due to
failure on its associated test.
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@mshockwave
mshockwave committed Jun 28, 2021
1 parent 616b998 commit 04242bd
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Showing 5 changed files with 4 additions and 249 deletions.
52 changes: 4 additions & 48 deletions llvm/lib/Target/M68k/GlSel/M68kCallLowering.cpp
View file
Expand Up @@ -15,17 +15,12 @@
#include "M68kCallLowering.h"
#include "M68kISelLowering.h"
#include "M68kInstrInfo.h"
#include "M68kSubtarget.h"
#include "M68kTargetMachine.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/TargetCallingConv.h"

using namespace llvm;

M68kCallLowering::M68kCallLowering(const M68kTargetLowering &TLI)
: CallLowering(&TLI) {}

bool M68kCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
const Value *Val, ArrayRef<Register> VRegs,
FunctionLoweringInfo &FLI,
Expand All @@ -41,50 +36,11 @@ bool M68kCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
const Function &F,
ArrayRef<ArrayRef<Register>> VRegs,
FunctionLoweringInfo &FLI) const {
MachineFunction &MF = MIRBuilder.getMF();
MachineRegisterInfo &MRI = MF.getRegInfo();
const auto &DL = F.getParent()->getDataLayout();
auto &TLI = *getTLI<M68kTargetLowering>();

SmallVector<ArgInfo, 8> SplitArgs;
unsigned I = 0;
for (const auto &Arg : F.args()) {
ArgInfo OrigArg{VRegs[I], Arg.getType()};
setArgFlags(OrigArg, I + AttributeList::FirstArgIndex, DL, F);
splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
++I;
}
if (F.arg_empty())
return true;

CCAssignFn *AssignFn =
TLI.getCCAssignFnForCall(F.getCallingConv(), false, F.isVarArg());
IncomingValueAssigner ArgAssigner(AssignFn);
FormalArgHandler ArgHandler(MIRBuilder, MRI);
return determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
MIRBuilder, F.getCallingConv(),
F.isVarArg());
}

void M68kIncomingValueHandler::assignValueToReg(Register ValVReg,
Register PhysReg,
CCValAssign &VA) {
MIRBuilder.getMRI()->addLiveIn(PhysReg);
MIRBuilder.getMBB().addLiveIn(PhysReg);
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
}

void M68kIncomingValueHandler::assignValueToAddress(Register ValVReg,
Register Addr,
uint64_t Size,
MachinePointerInfo &MPO,
CCValAssign &VA) {
llvm_unreachable("unimeplemented");
}

Register M68kIncomingValueHandler::getStackAddress(uint64_t Size,
int64_t Offset,
MachinePointerInfo &MPO,
ISD::ArgFlagsTy Flags) {
llvm_unreachable("unimeplemented");
return false;
}

bool M68kCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
Expand Down
23 changes: 0 additions & 23 deletions llvm/lib/Target/M68k/GlSel/M68kCallLowering.h
View file
Expand Up @@ -43,29 +43,6 @@ class M68kCallLowering : public CallLowering {

bool enableBigEndian() const override;
};
struct M68kIncomingValueHandler : public CallLowering::IncomingValueHandler {
M68kIncomingValueHandler(MachineIRBuilder &MIRBuilder,
MachineRegisterInfo &MRI)
: CallLowering::IncomingValueHandler(MIRBuilder, MRI) {}

uint64_t StackUsed;

private:
void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign &VA) override;

void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
MachinePointerInfo &MPO, CCValAssign &VA) override;

Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO,
ISD::ArgFlagsTy Flags) override;
};

struct FormalArgHandler : public M68kIncomingValueHandler {
FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
: M68kIncomingValueHandler(MIRBuilder, MRI) {}
};

} // end namespace llvm

Expand Down
6 changes: 0 additions & 6 deletions llvm/lib/Target/M68k/M68kISelLowering.cpp
View file
Expand Up @@ -3412,9 +3412,3 @@ const char *M68kTargetLowering::getTargetNodeName(unsigned Opcode) const {
return NULL;
}
}

CCAssignFn *M68kTargetLowering::getCCAssignFnForCall(CallingConv::ID CC,
bool Return,
bool IsVarArg) const {
return CC_M68k_C;
}
3 changes: 0 additions & 3 deletions llvm/lib/Target/M68k/M68kISelLowering.h
View file
Expand Up @@ -171,9 +171,6 @@ class M68kTargetLowering : public TargetLowering {
EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *MBB) const override;

CCAssignFn *getCCAssignFnForCall(CallingConv::ID CC, bool Return,
bool IsVarArg) const;

private:
unsigned GetAlignedArgumentStackSize(unsigned StackSize,
SelectionDAG &DAG) const;
Expand Down
169 changes: 0 additions & 169 deletions llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
View file
@@ -1,176 +1,7 @@
; RUN: llc -mtriple=m68k -global-isel -stop-after=irtranslator < %s | FileCheck %s

%struct.A = type { i8, float, i32, i32, i32 }

; CHECK: name: noArgRetVoid
; CHECK: RTS
define void @noArgRetVoid() {
ret void
}

define void @test_arg_lowering1(i8 %x, i8 %y) {
; CHECK-LABEL: name: test_arg_lowering1
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
; CHECK: [[G_TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD1]](s32)
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
; CHECK: [[G_TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD2]](s32)
; CHECK: RTS
ret void
}

define void @test_arg_lowering2(i16 %x, i16 %y) {
; CHECK-LABEL: name: test_arg_lowering2
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
; CHECK: [[G_TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[G_LOAD1]](s32)
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
; CHECK: [[G_TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[G_LOAD2]](s32)
; CHECK: RTS
ret void
}

define void @test_arg_lowering3(i32 %x, i32 %y) {
; CHECK-LABEL: name: test_arg_lowering3
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: {{%.*}} G_LOAD [[G_F_I1]](p0)
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: {{%.*}} G_LOAD [[G_F_I2]](p0)
; CHECK: RTS
ret void
}

define void @test_arg_lowering_vector(<5 x i8> %x) {
; CHECK-LABEL: name: test_arg_lowering_vector
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
; CHECK: [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
; CHECK: [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
; CHECK: [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[G_LOAD1]](s32), [[G_LOAD2]](s32), [[G_LOAD3]](s32), [[G_LOAD4]](s32), [[G_LOAD5]](s32)
; CHECK: [[G_TRUNC:%[0-9]+]]:_(<5 x s8>) = G_TRUNC [[BUILD_VECTOR]](<5 x s32>)
; CHECK: RTS
ret void
}

define void @test_arg_lowering_array([5 x i8] %x) {
; CHECK-LABEL: name: test_arg_lowering_array
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
; CHECK: [[G_TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD1]](s32)
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
; CHECK: [[G_TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD2]](s32)
; CHECK: [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
; CHECK: [[G_TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD3]](s32)
; CHECK: [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
; CHECK: [[G_TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD4]](s32)
; CHECK: [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
; CHECK: [[G_TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD5]](s32)
; CHECK: RTS
ret void
}

define void @test_arg_lowering_double(double %x) {
; CHECK-LABEL: name: test_arg_lowering_double
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
; CHECK: [[G_MERGE_VAL:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[G_LOAD1]](s32), [[G_LOAD2]](s32)
; CHECK: RTS
ret void
}

define void @test_arg_lowering_float(float %x) {
; CHECK-LABEL: name: test_arg_lowering_float
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
; CHECK: RTS
ret void
}

define void @test_arg_lowering_multiple(i1 %a, i8 %b, i16 %c, i32 %d, i64 %e, i128 %f){
; CHECK-LABEL: name: test_arg_lowering_multiple
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
; CHECK: [[G_TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[G_LOAD1]](s32)
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
; CHECK: [[G_TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD2]](s32)
; CHECK: [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
; CHECK: [[G_TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[G_LOAD3]](s32)
; CHECK: [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
; CHECK: [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
; CHECK: [[G_F_I6:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I6]](p0)
; CHECK: [[G_MERGE_VAL:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[G_LOAD5]](s32), [[G_LOAD6]](s32)
; CHECK: [[G_F_I7:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I7]](p0)
; CHECK: [[G_F_I8:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I8]](p0)
; CHECK: [[G_F_I9:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I9]](p0)
; CHECK: [[G_F_I10:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I10]](p0)
; CHECK: [[G_MERGE_VAL:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[G_LOAD7]](s32), [[G_LOAD8]](s32), [[G_LOAD9]](s32), [[G_LOAD10]](s32)
; CHECK: RTS
ret void
}

define void @test_arg_lowering_ptr(i32* %x) {
; CHECK-LABEL: name: test_arg_lowering_ptr
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[G_F_I1]](p0)
; CHECK: RTS
ret void
}

define void @test_arg_lowering_float_ptr(float* %x) {
; CHECK-LABEL: name: test_arg_lowering_float_ptr
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[G_F_I1]](p0)
; CHECK: RTS
ret void
}

define void @test_arg_lowering_struct(%struct.A %a) #0 {
; CHECK-LABEL: name: test_arg_lowering_struct
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
; CHECK: [[G_TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD1]](s32)
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
; CHECK: [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
; CHECK: [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
; CHECK: [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX
; CHECK: [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
; CHECK: RTS
ret void
}

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