[Clang][LoongArch] Add intrinsic for iocsrrd and iocsrwr

These intrinsics are required by Linux [1].

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h#n240

Differential Revision: https://reviews.llvm.org/D139612

clang/include/clang/Basic/BuiltinsLoongArch.def

@@ -38,5 +38,14 @@ TARGET_BUILTIN(__builtin_loongarch_csrwr_d, "ULiULiIUi", "nc", "64bit")
 TARGET_BUILTIN(__builtin_loongarch_csrxchg_w, "UiUiUiIUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_csrxchg_d, "ULiULiULiIUi", "nc", "64bit")
 
+TARGET_BUILTIN(__builtin_loongarch_iocsrrd_b, "UiUi", "nc", "")
+TARGET_BUILTIN(__builtin_loongarch_iocsrrd_h, "UiUi", "nc", "")
+TARGET_BUILTIN(__builtin_loongarch_iocsrrd_w, "UiUi", "nc", "")
+TARGET_BUILTIN(__builtin_loongarch_iocsrrd_d, "ULiUi", "nc", "64bit")
+TARGET_BUILTIN(__builtin_loongarch_iocsrwr_b, "vUiUi", "nc", "")
+TARGET_BUILTIN(__builtin_loongarch_iocsrwr_h, "vUiUi", "nc", "")
+TARGET_BUILTIN(__builtin_loongarch_iocsrwr_w, "vUiUi", "nc", "")
+TARGET_BUILTIN(__builtin_loongarch_iocsrwr_d, "vULiUi", "nc", "64bit")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/lib/CodeGen/CGBuiltin.cpp

@@ -19718,6 +19718,30 @@ Value *CodeGenFunction::EmitLoongArchBuiltinExpr(unsigned BuiltinID,
   case LoongArch::BI__builtin_loongarch_csrxchg_d:
     ID = Intrinsic::loongarch_csrxchg_d;
     break;
+  case LoongArch::BI__builtin_loongarch_iocsrrd_b:
+    ID = Intrinsic::loongarch_iocsrrd_b;
+    break;
+  case LoongArch::BI__builtin_loongarch_iocsrrd_h:
+    ID = Intrinsic::loongarch_iocsrrd_h;
+    break;
+  case LoongArch::BI__builtin_loongarch_iocsrrd_w:
+    ID = Intrinsic::loongarch_iocsrrd_w;
+    break;
+  case LoongArch::BI__builtin_loongarch_iocsrrd_d:
+    ID = Intrinsic::loongarch_iocsrrd_d;
+    break;
+  case LoongArch::BI__builtin_loongarch_iocsrwr_b:
+    ID = Intrinsic::loongarch_iocsrwr_b;
+    break;
+  case LoongArch::BI__builtin_loongarch_iocsrwr_h:
+    ID = Intrinsic::loongarch_iocsrwr_h;
+    break;
+  case LoongArch::BI__builtin_loongarch_iocsrwr_w:
+    ID = Intrinsic::loongarch_iocsrwr_w;
+    break;
+  case LoongArch::BI__builtin_loongarch_iocsrwr_d:
+    ID = Intrinsic::loongarch_iocsrwr_d;
+    break;
     // TODO: Support more Intrinsics.
   }
 

clang/lib/Headers/larchintrin.h

@@ -95,6 +95,58 @@ extern __inline int
       (unsigned long int)(_1), (unsigned long int)(_2), (_3)))
 #endif
 
+extern __inline unsigned char
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __iocsrrd_b(unsigned int _1) {
+  return (unsigned char)__builtin_loongarch_iocsrrd_b((unsigned int)_1);
+}
+
+extern __inline unsigned char
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __iocsrrd_h(unsigned int _1) {
+  return (unsigned short)__builtin_loongarch_iocsrrd_h((unsigned int)_1);
+}
+
+extern __inline unsigned int
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __iocsrrd_w(unsigned int _1) {
+  return (unsigned int)__builtin_loongarch_iocsrrd_w((unsigned int)_1);
+}
+
+#if __loongarch_grlen == 64
+extern __inline unsigned long int
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __iocsrrd_d(unsigned int _1) {
+  return (unsigned long int)__builtin_loongarch_iocsrrd_d((unsigned int)_1);
+}
+#endif
+
+extern __inline void
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __iocsrwr_b(unsigned char _1, unsigned int _2) {
+  __builtin_loongarch_iocsrwr_b((unsigned char)_1, (unsigned int)_2);
+}
+
+extern __inline void
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __iocsrwr_h(unsigned short _1, unsigned int _2) {
+  __builtin_loongarch_iocsrwr_h((unsigned short)_1, (unsigned int)_2);
+}
+
+extern __inline void
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __iocsrwr_w(unsigned int _1, unsigned int _2) {
+  __builtin_loongarch_iocsrwr_w((unsigned int)_1, (unsigned int)_2);
+}
+
+#if __loongarch_grlen == 64
+extern __inline void
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __iocsrwr_d(unsigned long int _1, unsigned int _2) {
+  __builtin_loongarch_iocsrwr_d((unsigned long int)_1, (unsigned int)_2);
+}
+#endif
+
 #ifdef __cplusplus
 }
 #endif

clang/lib/Sema/SemaChecking.cpp

@@ -3712,6 +3712,8 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
   case LoongArch::BI__builtin_loongarch_crcc_w_h_w:
   case LoongArch::BI__builtin_loongarch_crcc_w_w_w:
   case LoongArch::BI__builtin_loongarch_crcc_w_d_w:
+  case LoongArch::BI__builtin_loongarch_iocsrrd_d:
+  case LoongArch::BI__builtin_loongarch_iocsrwr_d:
     if (!TI.hasFeature("64bit"))
       return Diag(TheCall->getBeginLoc(),
                   diag::err_loongarch_builtin_requires_la64)

clang/test/CodeGen/LoongArch/intrinsic-la32-error.c

@@ -87,3 +87,11 @@ void csrxchg_w(unsigned int a, unsigned int b) {
     __builtin_loongarch_csrxchg_w(a, b, -1); // expected-error {{argument value 4294967295 is outside the valid range [0, 16383]}}
     __builtin_loongarch_csrxchg_w(a, b, b); // expected-error {{argument to '__builtin_loongarch_csrxchg_w' must be a constant integer}}
 }
+
+unsigned long int iocsrrd_d(unsigned int a) {
+  return __builtin_loongarch_iocsrrd_d(a); // expected-error {{this builtin requires target: loongarch64}}
+}
+
+void iocsrwr_d(unsigned long int a, unsigned int b) {
+  __builtin_loongarch_iocsrwr_d(a, b); // expected-error {{this builtin requires target: loongarch64}}
+}

clang/test/CodeGen/LoongArch/intrinsic-la32.c

@@ -107,3 +107,157 @@ unsigned int csrxchg_w(unsigned int a, unsigned int b) {
   unsigned int d = __builtin_loongarch_csrxchg_w(a, b, 1);
   return 0;
 }
+
+// LA32-LABEL: @iocsrrd_b(
+// LA32-NEXT:  entry:
+// LA32-NEXT:    [[_1_ADDR_I:%.*]] = alloca i32, align 4
+// LA32-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// LA32-NEXT:    [[B:%.*]] = alloca i8, align 1
+// LA32-NEXT:    [[C:%.*]] = alloca i8, align 1
+// LA32-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// LA32-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// LA32-NEXT:    store i32 [[TMP0]], ptr [[_1_ADDR_I]], align 4
+// LA32-NEXT:    [[TMP1:%.*]] = load i32, ptr [[_1_ADDR_I]], align 4
+// LA32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.loongarch.iocsrrd.b(i32 [[TMP1]])
+// LA32-NEXT:    [[CONV_I:%.*]] = trunc i32 [[TMP2]] to i8
+// LA32-NEXT:    store i8 [[CONV_I]], ptr [[B]], align 1
+// LA32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// LA32-NEXT:    [[TMP4:%.*]] = call i32 @llvm.loongarch.iocsrrd.b(i32 [[TMP3]])
+// LA32-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP4]] to i8
+// LA32-NEXT:    store i8 [[CONV]], ptr [[C]], align 1
+// LA32-NEXT:    ret i8 0
+//
+unsigned char iocsrrd_b(unsigned int a) {
+  unsigned char b = __iocsrrd_b(a);
+  unsigned char c = __builtin_loongarch_iocsrrd_b(a);
+  return 0;
+}
+
+// LA32-LABEL: @iocsrrd_h(
+// LA32-NEXT:  entry:
+// LA32-NEXT:    [[_1_ADDR_I:%.*]] = alloca i32, align 4
+// LA32-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// LA32-NEXT:    [[B:%.*]] = alloca i16, align 2
+// LA32-NEXT:    [[C:%.*]] = alloca i16, align 2
+// LA32-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// LA32-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// LA32-NEXT:    store i32 [[TMP0]], ptr [[_1_ADDR_I]], align 4
+// LA32-NEXT:    [[TMP1:%.*]] = load i32, ptr [[_1_ADDR_I]], align 4
+// LA32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.loongarch.iocsrrd.h(i32 [[TMP1]])
+// LA32-NEXT:    [[CONV_I:%.*]] = trunc i32 [[TMP2]] to i16
+// LA32-NEXT:    [[CONV1_I:%.*]] = trunc i16 [[CONV_I]] to i8
+// LA32-NEXT:    [[CONV:%.*]] = zext i8 [[CONV1_I]] to i16
+// LA32-NEXT:    store i16 [[CONV]], ptr [[B]], align 2
+// LA32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// LA32-NEXT:    [[TMP4:%.*]] = call i32 @llvm.loongarch.iocsrrd.h(i32 [[TMP3]])
+// LA32-NEXT:    [[CONV1:%.*]] = trunc i32 [[TMP4]] to i16
+// LA32-NEXT:    store i16 [[CONV1]], ptr [[C]], align 2
+// LA32-NEXT:    ret i16 0
+//
+unsigned short iocsrrd_h(unsigned int a) {
+  unsigned short b = __iocsrrd_h(a);
+  unsigned short c = __builtin_loongarch_iocsrrd_h(a);
+  return 0;
+}
+
+// LA32-LABEL: @iocsrrd_w(
+// LA32-NEXT:  entry:
+// LA32-NEXT:    [[_1_ADDR_I:%.*]] = alloca i32, align 4
+// LA32-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// LA32-NEXT:    [[B:%.*]] = alloca i32, align 4
+// LA32-NEXT:    [[C:%.*]] = alloca i32, align 4
+// LA32-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// LA32-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// LA32-NEXT:    store i32 [[TMP0]], ptr [[_1_ADDR_I]], align 4
+// LA32-NEXT:    [[TMP1:%.*]] = load i32, ptr [[_1_ADDR_I]], align 4
+// LA32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.loongarch.iocsrrd.w(i32 [[TMP1]])
+// LA32-NEXT:    store i32 [[TMP2]], ptr [[B]], align 4
+// LA32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// LA32-NEXT:    [[TMP4:%.*]] = call i32 @llvm.loongarch.iocsrrd.w(i32 [[TMP3]])
+// LA32-NEXT:    store i32 [[TMP4]], ptr [[C]], align 4
+// LA32-NEXT:    ret i32 0
+//
+unsigned int iocsrrd_w(unsigned int a) {
+  unsigned int b = __iocsrrd_w(a);
+  unsigned int c = __builtin_loongarch_iocsrrd_w(a);
+  return 0;
+}
+
+// LA32-LABEL: @iocsrwr_b(
+// LA32-NEXT:  entry:
+// LA32-NEXT:    [[_1_ADDR_I:%.*]] = alloca i8, align 1
+// LA32-NEXT:    [[_2_ADDR_I:%.*]] = alloca i32, align 4
+// LA32-NEXT:    [[A_ADDR:%.*]] = alloca i8, align 1
+// LA32-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
+// LA32-NEXT:    store i8 [[A:%.*]], ptr [[A_ADDR]], align 1
+// LA32-NEXT:    store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
+// LA32-NEXT:    [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1
+// LA32-NEXT:    [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// LA32-NEXT:    store i8 [[TMP0]], ptr [[_1_ADDR_I]], align 1
+// LA32-NEXT:    store i32 [[TMP1]], ptr [[_2_ADDR_I]], align 4
+// LA32-NEXT:    [[TMP2:%.*]] = load i8, ptr [[_1_ADDR_I]], align 1
+// LA32-NEXT:    [[CONV_I:%.*]] = zext i8 [[TMP2]] to i32
+// LA32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[_2_ADDR_I]], align 4
+// LA32-NEXT:    call void @llvm.loongarch.iocsrwr.b(i32 [[CONV_I]], i32 [[TMP3]])
+// LA32-NEXT:    [[TMP4:%.*]] = load i8, ptr [[A_ADDR]], align 1
+// LA32-NEXT:    [[CONV:%.*]] = zext i8 [[TMP4]] to i32
+// LA32-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// LA32-NEXT:    call void @llvm.loongarch.iocsrwr.b(i32 [[CONV]], i32 [[TMP5]])
+// LA32-NEXT:    ret void
+//
+void iocsrwr_b(unsigned char a, unsigned int b) {
+  __iocsrwr_b(a, b);
+  __builtin_loongarch_iocsrwr_b(a, b);
+}
+
+// LA32-LABEL: @iocsrwr_h(
+// LA32-NEXT:  entry:
+// LA32-NEXT:    [[_1_ADDR_I:%.*]] = alloca i16, align 2
+// LA32-NEXT:    [[_2_ADDR_I:%.*]] = alloca i32, align 4
+// LA32-NEXT:    [[A_ADDR:%.*]] = alloca i16, align 2
+// LA32-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
+// LA32-NEXT:    store i16 [[A:%.*]], ptr [[A_ADDR]], align 2
+// LA32-NEXT:    store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
+// LA32-NEXT:    [[TMP0:%.*]] = load i16, ptr [[A_ADDR]], align 2
+// LA32-NEXT:    [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// LA32-NEXT:    store i16 [[TMP0]], ptr [[_1_ADDR_I]], align 2
+// LA32-NEXT:    store i32 [[TMP1]], ptr [[_2_ADDR_I]], align 4
+// LA32-NEXT:    [[TMP2:%.*]] = load i16, ptr [[_1_ADDR_I]], align 2
+// LA32-NEXT:    [[CONV_I:%.*]] = zext i16 [[TMP2]] to i32
+// LA32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[_2_ADDR_I]], align 4
+// LA32-NEXT:    call void @llvm.loongarch.iocsrwr.h(i32 [[CONV_I]], i32 [[TMP3]])
+// LA32-NEXT:    [[TMP4:%.*]] = load i16, ptr [[A_ADDR]], align 2
+// LA32-NEXT:    [[CONV:%.*]] = zext i16 [[TMP4]] to i32
+// LA32-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// LA32-NEXT:    call void @llvm.loongarch.iocsrwr.h(i32 [[CONV]], i32 [[TMP5]])
+// LA32-NEXT:    ret void
+//
+void iocsrwr_h(unsigned short a, unsigned int b) {
+  __iocsrwr_h(a, b);
+  __builtin_loongarch_iocsrwr_h(a, b);
+}
+
+// LA32-LABEL: @iocsrwr_w(
+// LA32-NEXT:  entry:
+// LA32-NEXT:    [[_1_ADDR_I:%.*]] = alloca i32, align 4
+// LA32-NEXT:    [[_2_ADDR_I:%.*]] = alloca i32, align 4
+// LA32-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// LA32-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
+// LA32-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// LA32-NEXT:    store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
+// LA32-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// LA32-NEXT:    [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// LA32-NEXT:    store i32 [[TMP0]], ptr [[_1_ADDR_I]], align 4
+// LA32-NEXT:    store i32 [[TMP1]], ptr [[_2_ADDR_I]], align 4
+// LA32-NEXT:    [[TMP2:%.*]] = load i32, ptr [[_1_ADDR_I]], align 4
+// LA32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[_2_ADDR_I]], align 4
+// LA32-NEXT:    call void @llvm.loongarch.iocsrwr.w(i32 [[TMP2]], i32 [[TMP3]])
+// LA32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// LA32-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// LA32-NEXT:    call void @llvm.loongarch.iocsrwr.w(i32 [[TMP4]], i32 [[TMP5]])
+// LA32-NEXT:    ret void
+//
+void iocsrwr_w(unsigned int a, unsigned int b) {
+  __iocsrwr_w(a, b);
+  __builtin_loongarch_iocsrwr_w(a, b);
+}

clang/test/CodeGen/LoongArch/intrinsic-la64.c

@@ -222,3 +222,97 @@ unsigned long int csrxchg_d(unsigned long int a, unsigned long int b) {
   unsigned long int d = __builtin_loongarch_csrxchg_d(a, b, 1);
   return 0;
 }
+
+// CHECK-LABEL: @iocsrrd_b(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.b(i32 [[A:%.*]])
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.b(i32 [[A]])
+// CHECK-NEXT:    ret i8 0
+//
+unsigned char iocsrrd_b(unsigned int a) {
+  unsigned char b = __iocsrrd_b(a);
+  unsigned char c = __builtin_loongarch_iocsrrd_b(a);
+  return 0;
+}
+
+// CHECK-LABEL: @iocsrrd_h(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 [[A:%.*]])
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 [[A]])
+// CHECK-NEXT:    ret i16 0
+//
+unsigned short iocsrrd_h(unsigned int a) {
+  unsigned short b = __iocsrrd_h(a);
+  unsigned short c = __builtin_loongarch_iocsrrd_h(a);
+  return 0;
+}
+
+// CHECK-LABEL: @iocsrrd_w(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.w(i32 [[A:%.*]])
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.w(i32 [[A]])
+// CHECK-NEXT:    ret i32 0
+//
+unsigned int iocsrrd_w(unsigned int a) {
+  unsigned int b = __iocsrrd_w(a);
+  unsigned int c = __builtin_loongarch_iocsrrd_w(a);
+  return 0;
+}
+
+// CHECK-LABEL: @iocsrwr_b(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[CONV_I:%.*]] = zext i8 [[A:%.*]] to i32
+// CHECK-NEXT:    tail call void @llvm.loongarch.iocsrwr.b(i32 [[CONV_I]], i32 [[B:%.*]])
+// CHECK-NEXT:    tail call void @llvm.loongarch.iocsrwr.b(i32 [[CONV_I]], i32 [[B]])
+// CHECK-NEXT:    ret void
+//
+void iocsrwr_b(unsigned char a, unsigned int b) {
+  __iocsrwr_b(a, b);
+  __builtin_loongarch_iocsrwr_b(a, b);
+}
+
+// CHECK-LABEL: @iocsrwr_h(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[CONV_I:%.*]] = zext i16 [[A:%.*]] to i32
+// CHECK-NEXT:    tail call void @llvm.loongarch.iocsrwr.h(i32 [[CONV_I]], i32 [[B:%.*]])
+// CHECK-NEXT:    tail call void @llvm.loongarch.iocsrwr.h(i32 [[CONV_I]], i32 [[B]])
+// CHECK-NEXT:    ret void
+//
+void iocsrwr_h(unsigned short a, unsigned int b) {
+  __iocsrwr_h(a, b);
+  __builtin_loongarch_iocsrwr_h(a, b);
+}
+
+// CHECK-LABEL: @iocsrwr_w(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    tail call void @llvm.loongarch.iocsrwr.w(i32 [[A:%.*]], i32 [[B:%.*]])
+// CHECK-NEXT:    tail call void @llvm.loongarch.iocsrwr.w(i32 [[A]], i32 [[B]])
+// CHECK-NEXT:    ret void
+//
+void iocsrwr_w(unsigned int a, unsigned int b) {
+  __iocsrwr_w(a, b);
+  __builtin_loongarch_iocsrwr_w(a, b);
+}
+
+// CHECK-LABEL: @iocsrrd_d(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.loongarch.iocsrrd.d(i32 [[A:%.*]])
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call i64 @llvm.loongarch.iocsrrd.d(i32 [[A]])
+// CHECK-NEXT:    ret i64 0
+//
+unsigned long int iocsrrd_d(unsigned int a) {
+  unsigned long int b = __iocsrrd_d(a);
+  unsigned long int c = __builtin_loongarch_iocsrrd_d(a);
+  return 0;
+}
+
+// CHECK-LABEL: @iocsrwr_d(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    tail call void @llvm.loongarch.iocsrwr.d(i64 [[A:%.*]], i32 [[B:%.*]])
+// CHECK-NEXT:    tail call void @llvm.loongarch.iocsrwr.d(i64 [[A]], i32 [[B]])
+// CHECK-NEXT:    ret void
+//
+void iocsrwr_d(unsigned long int a, unsigned int b) {
+  __iocsrwr_d(a, b);
+  __builtin_loongarch_iocsrwr_d(a, b);
+}

llvm/include/llvm/IR/IntrinsicsLoongArch.td

@@ -92,4 +92,14 @@ def int_loongarch_csrxchg_d : Intrinsic<[llvm_i64_ty],
                                         [llvm_i64_ty, llvm_i64_ty,
                                          llvm_i32_ty],
                                         [ImmArg<ArgIndex<2>>]>;
+
+def int_loongarch_iocsrrd_b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>;
+def int_loongarch_iocsrrd_h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>;
+def int_loongarch_iocsrrd_w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>;
+def int_loongarch_iocsrrd_d : Intrinsic<[llvm_i64_ty], [llvm_i32_ty]>;
+
+def int_loongarch_iocsrwr_b : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty]>;
+def int_loongarch_iocsrwr_h : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty]>;
+def int_loongarch_iocsrwr_w : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty]>;
+def int_loongarch_iocsrwr_d : Intrinsic<[], [llvm_i64_ty, llvm_i32_ty]>;
 } // TargetPrefix = "loongarch"