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[TTI][AArch64] Cost model insertelement and indexed LD1 instructions
An indexed LD1 instruction, or "ASIMD load, 1 element, one lane, B/H/S" instruction that loads a value and inserts an element into a vector is an expensive instruction. It has a latency of 8 on modern cores. We generate an indexed LD1 when an insertelement instruction has a load as an operand and this patch is recognising and makes indexed LD1 more expensive. Differential Revision: https://reviews.llvm.org/D141602
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