[AArch64][SME] NFC: Pass target feature on RUN line, instead of funct…

…ion attribute. This is anticipating adding new RUN lines testing for +sme, alongside +sve/+sve2.
llvm · Jul 24, 2023 · 07d6502 · 07d6502
1 parent 6a51997
commit 07d6502
Show file tree

Hide file tree

Showing 57 changed files with 2,647 additions and 2,162 deletions.
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll
@@ -1,10 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ; i8
-define <4 x i8> @vls_sve_and_4xi8(<4 x i8> %b) nounwind #0 {
+define <4 x i8> @vls_sve_and_4xi8(<4 x i8> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_4xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI0_0
@@ -17,7 +17,7 @@ define <4 x i8> @vls_sve_and_4xi8(<4 x i8> %b) nounwind #0 {
  ret <4 x i8> %c
 }
 
-define <8 x i8> @vls_sve_and_8xi8(<8 x i8> %b) nounwind #0 {
+define <8 x i8> @vls_sve_and_8xi8(<8 x i8> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI1_0
@@ -30,7 +30,7 @@ define <8 x i8> @vls_sve_and_8xi8(<8 x i8> %b) nounwind #0 {
  ret <8 x i8> %c
 }
 
-define <16 x i8> @vls_sve_and_16xi8(<16 x i8> %b) nounwind #0 {
+define <16 x i8> @vls_sve_and_16xi8(<16 x i8> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI2_0
@@ -43,7 +43,7 @@ define <16 x i8> @vls_sve_and_16xi8(<16 x i8> %b) nounwind #0 {
  ret <16 x i8> %c
 }
 
-define <32 x i8> @vls_sve_and_32xi8(<32 x i8> %ap) nounwind #0 {
+define <32 x i8> @vls_sve_and_32xi8(<32 x i8> %ap) nounwind {
 ; CHECK-LABEL: vls_sve_and_32xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI3_0
@@ -61,7 +61,7 @@ define <32 x i8> @vls_sve_and_32xi8(<32 x i8> %ap) nounwind #0 {
 }
 
 ; i16
-define <2 x i16> @vls_sve_and_2xi16(<2 x i16> %b) nounwind #0 {
+define <2 x i16> @vls_sve_and_2xi16(<2 x i16> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_2xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -76,7 +76,7 @@ define <2 x i16> @vls_sve_and_2xi16(<2 x i16> %b) nounwind #0 {
  ret <2 x i16> %c
 }
 
-define <4 x i16> @vls_sve_and_4xi16(<4 x i16> %b) nounwind #0 {
+define <4 x i16> @vls_sve_and_4xi16(<4 x i16> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI5_0
@@ -89,7 +89,7 @@ define <4 x i16> @vls_sve_and_4xi16(<4 x i16> %b) nounwind #0 {
  ret <4 x i16> %c
 }
 
-define <8 x i16> @vls_sve_and_8xi16(<8 x i16> %b) nounwind #0 {
+define <8 x i16> @vls_sve_and_8xi16(<8 x i16> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI6_0
@@ -102,7 +102,7 @@ define <8 x i16> @vls_sve_and_8xi16(<8 x i16> %b) nounwind #0 {
  ret <8 x i16> %c
 }
 
-define <16 x i16> @vls_sve_and_16xi16(<16 x i16> %b) nounwind #0 {
+define <16 x i16> @vls_sve_and_16xi16(<16 x i16> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_16xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI7_0
@@ -119,7 +119,7 @@ define <16 x i16> @vls_sve_and_16xi16(<16 x i16> %b) nounwind #0 {
 }
 
 ; i32
-define <2 x i32> @vls_sve_and_2xi32(<2 x i32> %b) nounwind #0 {
+define <2 x i32> @vls_sve_and_2xi32(<2 x i32> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -131,7 +131,7 @@ define <2 x i32> @vls_sve_and_2xi32(<2 x i32> %b) nounwind #0 {
  ret <2 x i32> %c
 }
 
-define <4 x i32> @vls_sve_and_4xi32(<4 x i32> %b) nounwind #0 {
+define <4 x i32> @vls_sve_and_4xi32(<4 x i32> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI9_0
@@ -144,7 +144,7 @@ define <4 x i32> @vls_sve_and_4xi32(<4 x i32> %b) nounwind #0 {
  ret <4 x i32> %c
 }
 
-define <8 x i32> @vls_sve_and_8xi32(<8 x i32> %b) nounwind #0 {
+define <8 x i32> @vls_sve_and_8xi32(<8 x i32> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_8xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI10_0
@@ -161,7 +161,7 @@ define <8 x i32> @vls_sve_and_8xi32(<8 x i32> %b) nounwind #0 {
 }
 
 ; i64
-define <2 x i64> @vls_sve_and_2xi64(<2 x i64> %b) nounwind #0 {
+define <2 x i64> @vls_sve_and_2xi64(<2 x i64> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -173,7 +173,7 @@ define <2 x i64> @vls_sve_and_2xi64(<2 x i64> %b) nounwind #0 {
  ret <2 x i64> %c
 }
 
-define <4 x i64> @vls_sve_and_4xi64(<4 x i64> %b) nounwind #0 {
+define <4 x i64> @vls_sve_and_4xi64(<4 x i64> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_4xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
@@ -187,5 +187,3 @@ define <4 x i64> @vls_sve_and_4xi64(<4 x i64> %b) nounwind #0 {
  %c = and <4 x i64> %b, <i64 0, i64 18446744073709551615, i64 0, i64 18446744073709551615>
  ret <4 x i64> %c
 }
-
-attributes #0 = { "target-features"="+sve" }