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Revert "[InstCombine] enhance fold for subtract-from-constant -> xor"
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This reverts commit 79bb915.
This caused regressions because SCEV works better with sub.
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@rotateright
rotateright committed Jul 22, 2022
1 parent 70c62f4 commit 08091a9
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Showing 3 changed files with 27 additions and 27 deletions.
12 changes: 7 additions & 5 deletions llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
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Expand Up @@ -1966,12 +1966,14 @@ Instruction *InstCombinerImpl::visitSub(BinaryOperator &I) {
return BinaryOperator::CreateAdd(X, ConstantExpr::getSub(C, C2));
}

// If there's no chance any bit will need to borrow from an adjacent bit:
// sub C, X --> xor X, C
const APInt *Op0C;
if (match(Op0, m_APInt(Op0C)) &&
(~computeKnownBits(Op1, 0, &I).Zero).isSubsetOf(*Op0C))
return BinaryOperator::CreateXor(Op1, Op0);
if (match(Op0, m_APInt(Op0C)) && Op0C->isMask()) {
// Turn this into a xor if LHS is 2^n-1 and the remaining bits are known
// zero.
KnownBits RHSKnown = computeKnownBits(Op1, 0, &I);
if ((*Op0C | RHSKnown.Zero).isAllOnes())
return BinaryOperator::CreateXor(Op1, Op0);
}

{
Value *Y;
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6 changes: 2 additions & 4 deletions llvm/test/Transforms/InstCombine/sub-xor.ll
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Expand Up @@ -28,7 +28,7 @@ define <2 x i32> @low_mask_nsw_nuw_vec(<2 x i32> %x) {
define i8 @arbitrary_mask_sub_i8(i8 %x) {
; CHECK-LABEL: @arbitrary_mask_sub_i8(
; CHECK-NEXT: [[A:%.*]] = and i8 [[X:%.*]], 10
; CHECK-NEXT: [[M:%.*]] = xor i8 [[A]], 11
; CHECK-NEXT: [[M:%.*]] = sub nuw nsw i8 11, [[A]]
; CHECK-NEXT: ret i8 [[M]]
;
%a = and i8 %x, 10 ; 0b00001010
Expand Down Expand Up @@ -74,16 +74,14 @@ define i8 @arbitrary_mask_sub_nuw_high_bit_dont_care_i8(i8 %x) {
define <2 x i5> @arbitrary_mask_sub_v2i5(<2 x i5> %x) {
; CHECK-LABEL: @arbitrary_mask_sub_v2i5(
; CHECK-NEXT: [[A:%.*]] = and <2 x i5> [[X:%.*]], <i5 -8, i5 -8>
; CHECK-NEXT: [[M:%.*]] = xor <2 x i5> [[A]], <i5 -6, i5 -6>
; CHECK-NEXT: [[M:%.*]] = sub nuw nsw <2 x i5> <i5 -6, i5 -6>, [[A]]
; CHECK-NEXT: ret <2 x i5> [[M]]
;
%a = and <2 x i5> %x, <i5 24, i5 24> ; 0b11000
%m = sub <2 x i5> <i5 26, i5 26>, %a ; 0b11010
ret <2 x i5> %m
}

; negative test - sub constant isn't superset of masked bits

define i8 @not_masked_sub_i8(i8 %x) {
; CHECK-LABEL: @not_masked_sub_i8(
; CHECK-NEXT: [[A:%.*]] = and i8 [[X:%.*]], 7
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36 changes: 18 additions & 18 deletions llvm/test/Transforms/PhaseOrdering/SystemZ/sub-xor.ll
View file
Expand Up @@ -22,27 +22,27 @@ define dso_local zeroext i32 @foo(ptr noundef %a) #0 {
; CHECK-NEXT: [[ADD_PTR_110:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_19]]
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ADD_PTR_110]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[ADD_111:%.*]] = add i32 [[TMP1]], [[ADD]]
; CHECK-NEXT: [[IDX_NEG_216:%.*]] = xor i64 [[INDVARS_IV]], -2
; CHECK-NEXT: [[IDX_NEG_216:%.*]] = sub nuw nsw i64 -2, [[INDVARS_IV]]
; CHECK-NEXT: [[ADD_PTR_217:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_216]]
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ADD_PTR_217]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[ADD_218:%.*]] = add i32 [[TMP2]], [[ADD_111]]
; CHECK-NEXT: [[IDX_NEG_3:%.*]] = xor i64 [[INDVARS_IV]], -3
; CHECK-NEXT: [[IDX_NEG_3:%.*]] = sub nuw nsw i64 -3, [[INDVARS_IV]]
; CHECK-NEXT: [[ADD_PTR_3:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_3]]
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ADD_PTR_3]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[ADD_3:%.*]] = add i32 [[TMP3]], [[ADD_218]]
; CHECK-NEXT: [[IDX_NEG_4:%.*]] = xor i64 [[INDVARS_IV]], -4
; CHECK-NEXT: [[IDX_NEG_4:%.*]] = sub nuw nsw i64 -4, [[INDVARS_IV]]
; CHECK-NEXT: [[ADD_PTR_4:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_4]]
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ADD_PTR_4]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[ADD_4:%.*]] = add i32 [[TMP4]], [[ADD_3]]
; CHECK-NEXT: [[IDX_NEG_5:%.*]] = xor i64 [[INDVARS_IV]], -5
; CHECK-NEXT: [[IDX_NEG_5:%.*]] = sub nuw nsw i64 -5, [[INDVARS_IV]]
; CHECK-NEXT: [[ADD_PTR_5:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_5]]
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ADD_PTR_5]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[ADD_5:%.*]] = add i32 [[TMP5]], [[ADD_4]]
; CHECK-NEXT: [[IDX_NEG_6:%.*]] = xor i64 [[INDVARS_IV]], -6
; CHECK-NEXT: [[IDX_NEG_6:%.*]] = sub nuw nsw i64 -6, [[INDVARS_IV]]
; CHECK-NEXT: [[ADD_PTR_6:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_6]]
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ADD_PTR_6]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[ADD_6:%.*]] = add i32 [[TMP6]], [[ADD_5]]
; CHECK-NEXT: [[IDX_NEG_7:%.*]] = xor i64 [[INDVARS_IV]], -7
; CHECK-NEXT: [[IDX_NEG_7:%.*]] = sub nuw nsw i64 -7, [[INDVARS_IV]]
; CHECK-NEXT: [[ADD_PTR_7:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_7]]
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ADD_PTR_7]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[ADD_7]] = add i32 [[TMP7]], [[ADD_6]]
Expand All @@ -62,32 +62,32 @@ define dso_local zeroext i32 @foo(ptr noundef %a) #0 {
; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[ADD_PTR_1_1]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[MUL_1_1:%.*]] = shl i32 [[TMP9]], 1
; CHECK-NEXT: [[ADD_1_1:%.*]] = add i32 [[MUL_1_1]], [[ADD_1]]
; CHECK-NEXT: [[IDX_NEG_1_2:%.*]] = xor i64 [[INDVARS_IV_1]], -2
; CHECK-NEXT: [[IDX_NEG_1_2:%.*]] = sub nuw nsw i64 -2, [[INDVARS_IV_1]]
; CHECK-NEXT: [[ADD_PTR_1_2:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_1_2]]
; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[ADD_PTR_1_2]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[MUL_1_2:%.*]] = shl i32 [[TMP10]], 1
; CHECK-NEXT: [[ADD_1_2:%.*]] = add i32 [[MUL_1_2]], [[ADD_1_1]]
; CHECK-NEXT: [[IDX_NEG_1_3:%.*]] = xor i64 [[INDVARS_IV_1]], -3
; CHECK-NEXT: [[IDX_NEG_1_3:%.*]] = sub nuw nsw i64 -3, [[INDVARS_IV_1]]
; CHECK-NEXT: [[ADD_PTR_1_3:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_1_3]]
; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[ADD_PTR_1_3]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[MUL_1_3:%.*]] = shl i32 [[TMP11]], 1
; CHECK-NEXT: [[ADD_1_3:%.*]] = add i32 [[MUL_1_3]], [[ADD_1_2]]
; CHECK-NEXT: [[IDX_NEG_1_4:%.*]] = xor i64 [[INDVARS_IV_1]], -4
; CHECK-NEXT: [[IDX_NEG_1_4:%.*]] = sub nuw nsw i64 -4, [[INDVARS_IV_1]]
; CHECK-NEXT: [[ADD_PTR_1_4:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_1_4]]
; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[ADD_PTR_1_4]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[MUL_1_4:%.*]] = shl i32 [[TMP12]], 1
; CHECK-NEXT: [[ADD_1_4:%.*]] = add i32 [[MUL_1_4]], [[ADD_1_3]]
; CHECK-NEXT: [[IDX_NEG_1_5:%.*]] = xor i64 [[INDVARS_IV_1]], -5
; CHECK-NEXT: [[IDX_NEG_1_5:%.*]] = sub nuw nsw i64 -5, [[INDVARS_IV_1]]
; CHECK-NEXT: [[ADD_PTR_1_5:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_1_5]]
; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[ADD_PTR_1_5]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[MUL_1_5:%.*]] = shl i32 [[TMP13]], 1
; CHECK-NEXT: [[ADD_1_5:%.*]] = add i32 [[MUL_1_5]], [[ADD_1_4]]
; CHECK-NEXT: [[IDX_NEG_1_6:%.*]] = xor i64 [[INDVARS_IV_1]], -6
; CHECK-NEXT: [[IDX_NEG_1_6:%.*]] = sub nuw nsw i64 -6, [[INDVARS_IV_1]]
; CHECK-NEXT: [[ADD_PTR_1_6:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_1_6]]
; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[ADD_PTR_1_6]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[MUL_1_6:%.*]] = shl i32 [[TMP14]], 1
; CHECK-NEXT: [[ADD_1_6:%.*]] = add i32 [[MUL_1_6]], [[ADD_1_5]]
; CHECK-NEXT: [[IDX_NEG_1_7:%.*]] = xor i64 [[INDVARS_IV_1]], -7
; CHECK-NEXT: [[IDX_NEG_1_7:%.*]] = sub nuw nsw i64 -7, [[INDVARS_IV_1]]
; CHECK-NEXT: [[ADD_PTR_1_7:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_1_7]]
; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[ADD_PTR_1_7]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[MUL_1_7:%.*]] = shl i32 [[TMP15]], 1
Expand All @@ -108,32 +108,32 @@ define dso_local zeroext i32 @foo(ptr noundef %a) #0 {
; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[ADD_PTR_2_1]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[MUL_2_1:%.*]] = mul i32 [[TMP17]], 3
; CHECK-NEXT: [[ADD_2_1:%.*]] = add i32 [[MUL_2_1]], [[ADD_2]]
; CHECK-NEXT: [[IDX_NEG_2_2:%.*]] = xor i64 [[INDVARS_IV_2]], -2
; CHECK-NEXT: [[IDX_NEG_2_2:%.*]] = sub nuw nsw i64 -2, [[INDVARS_IV_2]]
; CHECK-NEXT: [[ADD_PTR_2_2:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_2_2]]
; CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[ADD_PTR_2_2]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[MUL_2_2:%.*]] = mul i32 [[TMP18]], 3
; CHECK-NEXT: [[ADD_2_2:%.*]] = add i32 [[MUL_2_2]], [[ADD_2_1]]
; CHECK-NEXT: [[IDX_NEG_2_3:%.*]] = xor i64 [[INDVARS_IV_2]], -3
; CHECK-NEXT: [[IDX_NEG_2_3:%.*]] = sub nuw nsw i64 -3, [[INDVARS_IV_2]]
; CHECK-NEXT: [[ADD_PTR_2_3:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_2_3]]
; CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[ADD_PTR_2_3]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[MUL_2_3:%.*]] = mul i32 [[TMP19]], 3
; CHECK-NEXT: [[ADD_2_3:%.*]] = add i32 [[MUL_2_3]], [[ADD_2_2]]
; CHECK-NEXT: [[IDX_NEG_2_4:%.*]] = xor i64 [[INDVARS_IV_2]], -4
; CHECK-NEXT: [[IDX_NEG_2_4:%.*]] = sub nuw nsw i64 -4, [[INDVARS_IV_2]]
; CHECK-NEXT: [[ADD_PTR_2_4:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_2_4]]
; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[ADD_PTR_2_4]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[MUL_2_4:%.*]] = mul i32 [[TMP20]], 3
; CHECK-NEXT: [[ADD_2_4:%.*]] = add i32 [[MUL_2_4]], [[ADD_2_3]]
; CHECK-NEXT: [[IDX_NEG_2_5:%.*]] = xor i64 [[INDVARS_IV_2]], -5
; CHECK-NEXT: [[IDX_NEG_2_5:%.*]] = sub nuw nsw i64 -5, [[INDVARS_IV_2]]
; CHECK-NEXT: [[ADD_PTR_2_5:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_2_5]]
; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[ADD_PTR_2_5]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[MUL_2_5:%.*]] = mul i32 [[TMP21]], 3
; CHECK-NEXT: [[ADD_2_5:%.*]] = add i32 [[MUL_2_5]], [[ADD_2_4]]
; CHECK-NEXT: [[IDX_NEG_2_6:%.*]] = xor i64 [[INDVARS_IV_2]], -6
; CHECK-NEXT: [[IDX_NEG_2_6:%.*]] = sub nuw nsw i64 -6, [[INDVARS_IV_2]]
; CHECK-NEXT: [[ADD_PTR_2_6:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_2_6]]
; CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[ADD_PTR_2_6]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[MUL_2_6:%.*]] = mul i32 [[TMP22]], 3
; CHECK-NEXT: [[ADD_2_6:%.*]] = add i32 [[MUL_2_6]], [[ADD_2_5]]
; CHECK-NEXT: [[IDX_NEG_2_7:%.*]] = xor i64 [[INDVARS_IV_2]], -7
; CHECK-NEXT: [[IDX_NEG_2_7:%.*]] = sub nuw nsw i64 -7, [[INDVARS_IV_2]]
; CHECK-NEXT: [[ADD_PTR_2_7:%.*]] = getelementptr inbounds i32, ptr getelementptr inbounds ([100 x i32], ptr @ARR, i64 0, i64 99), i64 [[IDX_NEG_2_7]]
; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[ADD_PTR_2_7]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[MUL_2_7:%.*]] = mul i32 [[TMP23]], 3
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