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Reland [AMDGPU] gfx11 VOP1+VOP2 Instruction MC support
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The reverted dependent commit is now relanded, so reland this.
Includes dpp instructions and vop1/vop2 promoted to vop3

Patch 17/N for upstreaming of AMDGPU gfx11 architecture

Depends on D126483

Reviewed By: rampitec, #amdgpu

Differential Revision: https://reviews.llvm.org/D126917
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@Sisyph
Sisyph committed Jun 8, 2022
1 parent 9d6d069 commit 086a9c1
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Showing 13 changed files with 21,894 additions and 10,878 deletions.
5 changes: 4 additions & 1 deletion llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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Expand Up @@ -8173,9 +8173,12 @@ void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
Opc == AMDGPU::V_MAC_F16_e64_vi ||
Opc == AMDGPU::V_FMAC_F64_e64_gfx90a ||
Opc == AMDGPU::V_FMAC_F32_e64_gfx10 ||
Opc == AMDGPU::V_FMAC_F32_e64_gfx11 ||
Opc == AMDGPU::V_FMAC_F32_e64_vi ||
Opc == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 ||
Opc == AMDGPU::V_FMAC_F16_e64_gfx10) {
Opc == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 ||
Opc == AMDGPU::V_FMAC_F16_e64_gfx10 ||
Opc == AMDGPU::V_FMAC_F16_e64_gfx11) {
auto it = Inst.begin();
std::advance(it, AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers));
it = Inst.insert(it, MCOperand::createImm(0)); // no modifiers for src2
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13 changes: 12 additions & 1 deletion llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
View file
Expand Up @@ -465,12 +465,20 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
break;
MI = MCInst(); // clear

Res = tryDecodeInst(DecoderTableDPP8GFX1164, MI, QW, Address);
if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
break;
MI = MCInst(); // clear

Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
if (Res) break;

Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address);
if (Res)
break;

Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
if (Res) { IsSDWA = true; break; }

Expand Down Expand Up @@ -561,8 +569,11 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a ||
MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx11 ||
MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 ||
MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
MI.getOpcode() == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 ||
MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10 ||
MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx11)) {
// Insert dummy unused src2_modifiers.
insertNamedMCOperand(MI, MCOperand::createImm(0),
AMDGPU::OpName::src2_modifiers);
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41 changes: 32 additions & 9 deletions llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
View file
Expand Up @@ -400,7 +400,16 @@ void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
printDefaultVccOperand(1, STI, O);
case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
printDefaultVccOperand(false, STI, O);
break;
}
}
Expand Down Expand Up @@ -583,14 +592,16 @@ void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
O << " abid:" << Imm;
}

void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo,
void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
const MCSubtargetInfo &STI,
raw_ostream &O) {
if (OpNo > 0)
if (!FirstOperand)
O << ", ";
printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);
if (OpNo == 0)
printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]
? AMDGPU::VCC
: AMDGPU::VCC_LO,
O, MRI);
if (FirstOperand)
O << ", ";
}

Expand Down Expand Up @@ -623,7 +634,7 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
(Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
printDefaultVccOperand(OpNo, STI, O);
printDefaultVccOperand(true, STI, O);

if (OpNo >= MI->getNumOperands()) {
O << "/*Missing OP" << OpNo << "*/";
Expand Down Expand Up @@ -743,12 +754,24 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
case AMDGPU::V_CNDMASK_B32_e32_gfx11:
case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:

case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
case AMDGPU::V_CNDMASK_B32_e32_vi:
if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
AMDGPU::OpName::src1))
printDefaultVccOperand(OpNo, STI, O);
printDefaultVccOperand(OpNo == 0, STI, O);
break;
}

Expand Down Expand Up @@ -817,7 +840,7 @@ void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
AMDGPU::OpName::src1))
printDefaultVccOperand(OpNo, STI, O);
printDefaultVccOperand(OpNo == 0, STI, O);
break;
}
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
View file
Expand Up @@ -173,7 +173,7 @@ class AMDGPUInstPrinter : public MCInstPrinter {
raw_ostream &O);
void printABID(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printDefaultVccOperand(unsigned OpNo, const MCSubtargetInfo &STI,
void printDefaultVccOperand(bool FirstOperand, const MCSubtargetInfo &STI,
raw_ostream &O);
void printWaitVDST(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/SIInstrInfo.td
View file
Expand Up @@ -2551,10 +2551,10 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableF32SrcMods = 0,
class VOP_PAT_GEN <VOPProfile p, int mode=PatGenMode.NoPattern> : VOPProfile <p.ArgVT> {
let NeedPatGen = mode;
}

def VOP_F16_F16 : VOPProfile <[f16, f16, untyped, untyped]>;
def VOP_F16_I16 : VOPProfile <[f16, i16, untyped, untyped]>;
def VOP_I16_F16 : VOPProfile <[i16, f16, untyped, untyped]>;
def VOP_I16_I16 : VOPProfile <[i16, i16, untyped, untyped]>;

def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i16, untyped]>;
Expand All @@ -2566,6 +2566,7 @@ def VOP_I16_I16_I16_I16 : VOPProfile <[i16, i16, i16, i16, untyped]>;
def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>;

def VOP_I32_I16_I16_I32 : VOPProfile <[i32, i16, i16, i32, untyped]>;
def VOP_I32_I16 : VOPProfile <[i32, i16, untyped, untyped]>;

def VOP_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, untyped]>;
def VOP_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, untyped]>;
Expand Down

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