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AMDGPU: Add a MIR test to catch infinite loop
This is derived from one of the regressions reported after aed1a2217a1da0c9fb7d2c0856302dee25b1d4a1
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llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
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|---|---|---|
| @@ -0,0 +1,143 @@ | ||
| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 | ||
| # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-regalloc -start-before=greedy,0 -stop-after=virtregrewriter,0 -simplify-mir -o - %s | FileCheck %s | ||
|
|
||
| --- | | ||
|
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||
| define void @main() #0 { | ||
| bb: | ||
| ret void | ||
| } | ||
|
|
||
| attributes #0 = { "amdgpu-waves-per-eu"="10,10" } | ||
|
|
||
| ... | ||
| --- | ||
| name: main | ||
| tracksRegLiveness: true | ||
| machineFunctionInfo: | ||
| scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' | ||
| frameOffsetReg: '$sgpr33' | ||
| stackPtrOffsetReg: '$sgpr32' | ||
| occupancy: 8 | ||
| sgprForEXECCopy: '$sgpr58_sgpr59' | ||
| body: | | ||
| ; CHECK-LABEL: name: main | ||
| ; CHECK: bb.0: | ||
| ; CHECK-NEXT: liveins: $vgpr0 | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: renamable $sgpr5 = IMPLICIT_DEF | ||
| ; CHECK-NEXT: dead undef [[DEF:%[0-9]+]].sub0:vreg_64 = IMPLICIT_DEF | ||
| ; CHECK-NEXT: dead [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF | ||
| ; CHECK-NEXT: dead undef [[DEF2:%[0-9]+]].sub0:vreg_64 = IMPLICIT_DEF | ||
| ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = S_LOAD_DWORDX16_IMM renamable $sgpr4_sgpr5, 0, 0 :: (invariant load (s512), align 32, addrspace 4) | ||
| ; CHECK-NEXT: renamable $sgpr24 = IMPLICIT_DEF | ||
| ; CHECK-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = S_LOAD_DWORDX16_IMM undef renamable $sgpr4_sgpr5, 0, 0 :: (invariant load (s512), align 32, addrspace 4) | ||
| ; CHECK-NEXT: $exec = S_MOV_B64_term undef renamable $sgpr4_sgpr5 | ||
| ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.6, implicit $exec | ||
| ; CHECK-NEXT: S_BRANCH %bb.5 | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: bb.1: | ||
| ; CHECK-NEXT: liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x000000000000FFFF | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: $exec = S_MOV_B64_term undef renamable $sgpr4_sgpr5 | ||
| ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.4, implicit $exec | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: bb.2: | ||
| ; CHECK-NEXT: liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x000000000000FFFF | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: dead [[IMAGE_SAMPLE_LZ_V1_V2_:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF2]], killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43, undef renamable $sgpr24_sgpr25_sgpr26_sgpr27, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) | ||
| ; CHECK-NEXT: dead [[IMAGE_SAMPLE_LZ_V1_V2_1:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF2]], killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, renamable $sgpr24_sgpr25_sgpr26_sgpr27, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: bb.3: | ||
| ; CHECK-NEXT: SI_RETURN | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: bb.4: | ||
| ; CHECK-NEXT: liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x000000000000FFFF | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: renamable $sgpr12 = IMPLICIT_DEF | ||
| ; CHECK-NEXT: SI_SPILL_S512_SAVE renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s512) into %stack.0, align 4, addrspace 5) | ||
| ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = IMPLICIT_DEF | ||
| ; CHECK-NEXT: dead undef [[IMAGE_SAMPLE_LZ_V1_V2_2:%[0-9]+]].sub0:vreg_96 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF2]], killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43, renamable $sgpr12_sgpr13_sgpr14_sgpr15, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) | ||
| ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = SI_SPILL_S512_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s512) from %stack.0, align 4, addrspace 5) | ||
| ; CHECK-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = IMPLICIT_DEF | ||
| ; CHECK-NEXT: dead undef [[IMAGE_SAMPLE_LZ_V1_V2_3:%[0-9]+]].sub0:vreg_128 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF2]], undef renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, killed renamable $sgpr12_sgpr13_sgpr14_sgpr15, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) | ||
| ; CHECK-NEXT: S_BRANCH %bb.2 | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: bb.5: | ||
| ; CHECK-NEXT: liveins: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x00000000FFFFFFFF | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 = COPY killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 | ||
| ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = IMPLICIT_DEF | ||
| ; CHECK-NEXT: dead [[IMAGE_SAMPLE_LZ_V1_V2_4:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF]], killed renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, undef renamable $sgpr24_sgpr25_sgpr26_sgpr27, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) | ||
| ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = COPY killed renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 | ||
| ; CHECK-NEXT: S_BRANCH %bb.7 | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: bb.6: | ||
| ; CHECK-NEXT: liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x000000000000FFFF | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, undef renamable $sgpr4_sgpr5, implicit-def $scc | ||
| ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.8, implicit $exec | ||
| ; CHECK-NEXT: S_BRANCH %bb.1 | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: bb.7: | ||
| ; CHECK-NEXT: liveins: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x00000000FFFFFFFF | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: dead [[IMAGE_SAMPLE_LZ_V1_V2_5:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF]], renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, undef renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) | ||
| ; CHECK-NEXT: renamable $sgpr25 = COPY undef renamable $sgpr24 | ||
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.7, implicit undef $vcc | ||
| ; CHECK-NEXT: S_BRANCH %bb.6 | ||
| ; CHECK-NEXT: {{ $}} | ||
| ; CHECK-NEXT: bb.8: | ||
| ; CHECK-NEXT: SI_RETURN | ||
| bb.0: | ||
| liveins: $vgpr0 | ||
| undef %0.sub1:sreg_64 = IMPLICIT_DEF | ||
| %1:sgpr_512 = IMPLICIT_DEF | ||
| dead undef %2.sub0:vreg_64 = IMPLICIT_DEF | ||
| %3:sgpr_256 = IMPLICIT_DEF | ||
| dead %4:vgpr_32 = IMPLICIT_DEF | ||
| dead undef %5.sub0:vreg_64 = IMPLICIT_DEF | ||
| %6:sgpr_512 = S_LOAD_DWORDX16_IMM %0, 0, 0 :: (invariant load (s512), align 32, addrspace 4) | ||
| undef %7.sub0:sgpr_128 = IMPLICIT_DEF | ||
| %8:sgpr_512 = S_LOAD_DWORDX16_IMM undef %0, 0, 0 :: (invariant load (s512), align 32, addrspace 4) | ||
| $exec = S_MOV_B64_term undef %0 | ||
| S_CBRANCH_EXECZ %bb.6, implicit $exec | ||
| S_BRANCH %bb.5 | ||
| bb.1: | ||
| $exec = S_MOV_B64_term undef %0 | ||
| S_CBRANCH_EXECNZ %bb.4, implicit $exec | ||
| bb.2: | ||
| dead %9:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %5, %6.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, undef %7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) | ||
| dead %10:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %5, %8.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, %7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) | ||
| bb.3: | ||
| SI_RETURN | ||
| bb.4: | ||
| undef %11.sub0:sgpr_128 = IMPLICIT_DEF | ||
| dead undef %12.sub0:vreg_96 = IMAGE_SAMPLE_LZ_V1_V2 undef %5, %1.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, %11, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) | ||
| dead undef %13.sub0:vreg_128 = IMAGE_SAMPLE_LZ_V1_V2 undef %5, undef %6.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, %3.sub0_sub1_sub2_sub3, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) | ||
| S_BRANCH %bb.2 | ||
| bb.5: | ||
| dead %14:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %2, %1.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, undef %7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) | ||
| S_BRANCH %bb.7 | ||
| bb.6: | ||
| $exec = S_XOR_B64_term $exec, undef %0, implicit-def $scc | ||
| S_CBRANCH_EXECZ %bb.8, implicit $exec | ||
| S_BRANCH %bb.1 | ||
| bb.7: | ||
| dead %15:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %2, %6.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, undef %3.sub4_sub5_sub6_sub7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) | ||
| undef %7.sub1:sgpr_128 = COPY undef %7.sub0 | ||
| S_CBRANCH_VCCNZ %bb.7, implicit undef $vcc | ||
| S_BRANCH %bb.6 | ||
| bb.8: | ||
| SI_RETURN | ||
| ... |