[RISCV] Move Zca/Zcb/Zcd/Zcf/Zcmp/Zcmt out of experimental status.

According to https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
these were ratified in April 2023.

Reviewed By: VincentWu

Differential Revision: https://reviews.llvm.org/D153161

clang/test/Driver/riscv-arch.c

@@ -373,24 +373,24 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
 // RV32-ZFHMIN: "-target-feature" "+zfhmin"
 
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32izca -### %s \
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfa -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
-// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izca'
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izfa'
 // RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
 
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32izca -menable-experimental-extensions -### %s \
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfa -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
-// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izca'
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izfa'
 // RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number
 
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32izca0p1 -menable-experimental-extensions -### %s \
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfa0p1 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
-// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izca0p1'
-// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension 'zca' (this compiler supports 1.0)
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izfa0p1'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension 'zfa' (this compiler supports 0.2)
 
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32izca1p0 -menable-experimental-extensions -### %s \
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfa0p2 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
-// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zca"
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zfa"
 
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s

llvm/docs/RISCVUsage.rst

@@ -100,6 +100,12 @@ on support follow.
      ``Zbkc``         Supported
      ``Zbkx``         Supported (`See note <#riscv-scalar-crypto-note1>`__)
      ``Zbs``          Supported
+     ``Zca``          Supported
+     ``Zcb``          Supported
+     ``Zcd``          Supported
+     ``Zcf``          Supported
+     ``Zcmp``         Assembly Support
+     ``Zcmt``         Assembly Support
      ``Zdinx``        Supported
      ``Zfh``          Supported
      ``Zfhmin``       Supported
@@ -183,24 +189,6 @@ The primary goal of experimental support is to assist in the process of ratifica
 ``experimental-ssaia``
   LLVM implements the `Ratification candidate 3 <https://github.com/riscv/riscv-aia/releases/tag/1.0-RC3>`_.
 
-``experimental-zca``
-  LLVM implements the `1.0.1 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.1>`__.
-
-``experimental-zcb``
-  LLVM implements the `1.0.1 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.1>`__.
-
-``experimental-zcd``
-  LLVM implements the `1.0.1 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.1>`__.
-
-``experimental-zcf``
-  LLVM implements the `1.0.1 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.1>`__.
-
-``experimental-zcmp``
-  LLVM implements the `1.0.1 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.1>`__.
-
-``experimental-zcmt``
-  LLVM implements the `1.0.1 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.1>`_.
-
 ``experimental-zfa``
   LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20230131-c0b298a/zfa-20230414.pdf>`__.
 

llvm/lib/Support/RISCVISAInfo.cpp

@@ -56,6 +56,13 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 
     {"zihintpause", RISCVExtensionVersion{2, 0}},
 
+    {"zca", RISCVExtensionVersion{1, 0}},
+    {"zcb", RISCVExtensionVersion{1, 0}},
+    {"zcd", RISCVExtensionVersion{1, 0}},
+    {"zcf", RISCVExtensionVersion{1, 0}},
+    {"zcmp", RISCVExtensionVersion{1, 0}},
+    {"zcmt", RISCVExtensionVersion{1, 0}},
+
     {"zfhmin", RISCVExtensionVersion{1, 0}},
     {"zfh", RISCVExtensionVersion{1, 0}},
 
@@ -140,12 +147,6 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
 
     {"zihintntl", RISCVExtensionVersion{0, 2}},
 
-    {"zca", RISCVExtensionVersion{1, 0}},
-    {"zcb", RISCVExtensionVersion{1, 0}},
-    {"zcd", RISCVExtensionVersion{1, 0}},
-    {"zcf", RISCVExtensionVersion{1, 0}},
-    {"zcmp", RISCVExtensionVersion{1, 0}},
-    {"zcmt", RISCVExtensionVersion{1, 0}},
     {"zfa", RISCVExtensionVersion{0, 2}},
     {"zfbfmin", RISCVExtensionVersion{0, 6}},
     {"zicond", RISCVExtensionVersion{1, 0}},

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -2803,7 +2803,7 @@ bool RISCVAsmParser::parseDirectiveOption() {
 
     getTargetStreamer().emitDirectiveOptionNoRVC();
     clearFeatureBits(RISCV::FeatureStdExtC, "c");
-    clearFeatureBits(RISCV::FeatureStdExtZca, "+experimental-zca");
+    clearFeatureBits(RISCV::FeatureStdExtZca, "+zca");
     return false;
   }
 

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -323,7 +323,7 @@ def FeatureStdExtZk
                         FeatureStdExtZkt]>;
 
 def FeatureStdExtZca
-    : SubtargetFeature<"experimental-zca", "HasStdExtZca", "true",
+    : SubtargetFeature<"zca", "HasStdExtZca", "true",
                        "'Zca' (part of the C extension, excluding compressed "
                        "floating point loads/stores)">;
 
@@ -335,15 +335,15 @@ def HasStdExtCOrZca
                                    "compressed floating point loads/stores)">;
 
 def FeatureStdExtZcb
-    : SubtargetFeature<"experimental-zcb", "HasStdExtZcb", "true",
+    : SubtargetFeature<"zcb", "HasStdExtZcb", "true",
                        "'Zcb' (Compressed basic bit manipulation instructions)",
                        [FeatureStdExtZca]>;
 def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
                              AssemblerPredicate<(all_of FeatureStdExtZcb),
                              "'Zcb' (Compressed basic bit manipulation instructions)">;
 
 def FeatureStdExtZcd
-    : SubtargetFeature<"experimental-zcd", "HasStdExtZcd", "true",
+    : SubtargetFeature<"zcd", "HasStdExtZcd", "true",
                        "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
 
 def HasStdExtCOrZcd
@@ -353,7 +353,7 @@ def HasStdExtCOrZcd
                                    "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
 
 def FeatureStdExtZcf
-    : SubtargetFeature<"experimental-zcf", "HasStdExtZcf", "true",
+    : SubtargetFeature<"zcf", "HasStdExtZcf", "true",
                        "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
 
 def HasStdExtCOrZcf
@@ -363,15 +363,15 @@ def HasStdExtCOrZcf
                                    "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
 
 def FeatureStdExtZcmp
-    : SubtargetFeature<"experimental-zcmp", "HasStdExtZcmp", "true",
+    : SubtargetFeature<"zcmp", "HasStdExtZcmp", "true",
                        "'Zcmp' (sequenced instuctions for code-size reduction)", 
                        [FeatureStdExtZca]>;
 def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
                                AssemblerPredicate<(all_of FeatureStdExtZcmp, (not FeatureStdExtC)),
                                "'Zcmp' (sequenced instuctions for code-size reduction)">;
 
 def FeatureStdExtZcmt
-    : SubtargetFeature<"experimental-zcmt", "HasStdExtZcmt", "true",
+    : SubtargetFeature<"zcmt", "HasStdExtZcmt", "true",
                        "'Zcmt' (table jump instuctions for code-size reduction)", 
                        [FeatureStdExtZca, FeatureStdExtZicsr]>; 
 def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,

llvm/test/CodeGen/RISCV/add-before-shl.ll

@@ -7,9 +7,9 @@
 ; RUN:   < %s | FileCheck -check-prefixes=RV32C %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c -verify-machineinstrs --riscv-no-aliases \
 ; RUN:   < %s | FileCheck -check-prefixes=RV64C %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca -verify-machineinstrs --riscv-no-aliases \
+; RUN: llc -mtriple=riscv32 -mattr=+zca -verify-machineinstrs --riscv-no-aliases \
 ; RUN:   < %s | FileCheck -check-prefixes=RV32C %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca -verify-machineinstrs --riscv-no-aliases \
+; RUN: llc -mtriple=riscv64 -mattr=+zca -verify-machineinstrs --riscv-no-aliases \
 ; RUN:   < %s | FileCheck -check-prefixes=RV64C %s
 
 ; These test that constant adds are not moved after shifts by DAGCombine,

llvm/test/CodeGen/RISCV/attributes.ll

@@ -48,11 +48,12 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmemidx %s -o - | FileCheck --check-prefix=RV32XTHEADMEMIDX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV32XTHEADMEMPAIR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV32XTHEADSYNC %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCA %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCB %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCD %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCF %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmt %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCMT %s
+; RUN: llc -mtriple=riscv32 -mattr=+zca %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCA %s
+; RUN: llc -mtriple=riscv32 -mattr=+zcb %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zcd %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCD %s
+; RUN: llc -mtriple=riscv32 -mattr=+zcf %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zcmp %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCMP %s
+; RUN: llc -mtriple=riscv32 -mattr=+zcmt %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCMT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICSR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICNTR %s
@@ -135,10 +136,11 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADVDOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zawrs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefixes=CHECK,RV64ZTSO %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCA %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCB %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmt %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMT %s
+; RUN: llc -mtriple=riscv64 -mattr=+zca %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCA %s
+; RUN: llc -mtriple=riscv64 -mattr=+zcb %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCB %s
+; RUN: llc -mtriple=riscv64 -mattr=+zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s
+; RUN: llc -mtriple=riscv64 -mattr=+zcmp %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMP %s
+; RUN: llc -mtriple=riscv64 -mattr=+zcmt %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICSR %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICNTR %s
@@ -219,6 +221,7 @@
 ; RV32ZCB: .attribute 5, "rv32i2p1_zca1p0_zcb1p0"
 ; RV32ZCD: .attribute 5, "rv32i2p1_zcd1p0"
 ; RV32ZCF: .attribute 5, "rv32i2p1_zcf1p0"
+; RV32ZCMP: .attribute 5, "rv32i2p1_zca1p0_zcmp1p0"
 ; RV32ZCMT: .attribute 5, "rv32i2p1_zicsr2p0_zca1p0_zcmt1p0"
 ; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0"
 ; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0"
@@ -304,6 +307,7 @@
 ; RV64ZCA: .attribute 5, "rv64i2p1_zca1p0"
 ; RV64ZCB: .attribute 5, "rv64i2p1_zca1p0_zcb1p0"
 ; RV64ZCD: .attribute 5, "rv64i2p1_zcd1p0"
+; RV64ZCMP: .attribute 5, "rv64i2p1_zca1p0_zcmp1p0"
 ; RV64ZCMT: .attribute 5, "rv64i2p1_zicsr2p0_zca1p0_zcmt1p0"
 ; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0"
 ; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0"

llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll

@@ -1,11 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECK32I %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmp -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+zcmp -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECK32ZCMP %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECK64I %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmp -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zcmp -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECK64ZCMP %s
 
 declare i32 @foo(i32)

llvm/test/MC/RISCV/align.s

@@ -22,10 +22,10 @@
 # RUN:     | llvm-readobj -r - | FileCheck -check-prefix=C-OR-ZCA-EXT-RELAX-RELOC %s
 
 # Relaxation enabled with Zca extension:
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zca,+relax < %s \
-# RUN:     | llvm-objdump --mattr=+experimental-zca -d -M no-aliases - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zca,+relax < %s \
+# RUN:     | llvm-objdump --mattr=+zca -d -M no-aliases - \
 # RUN:     | FileCheck -check-prefix=C-OR-ZCA-EXT-RELAX-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zca,+relax < %s \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zca,+relax < %s \
 # RUN:     | llvm-readobj -r - | FileCheck -check-prefix=C-OR-ZCA-EXT-RELAX-RELOC %s
 
 # Relaxation disabled with C extension:
@@ -36,10 +36,10 @@
 # RUN:     | llvm-readobj -r - | FileCheck -check-prefix=C-OR-ZCA-EXT-NORELAX-RELOC %s
 
 # Relaxation disabled with ZCA extension:
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zca,-relax < %s \
-# RUN:     | llvm-objdump --mattr=+experimental-zca -d -M no-aliases - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zca,-relax < %s \
+# RUN:     | llvm-objdump --mattr=+zca -d -M no-aliases - \
 # RUN:     | FileCheck -check-prefix=C-OR-ZCA-EXT-NORELAX-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zca,-relax < %s \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zca,-relax < %s \
 # RUN:     | llvm-readobj -r - | FileCheck -check-prefix=C-OR-ZCA-EXT-NORELAX-RELOC %s
 
 # We need to insert N-MinNopSize bytes NOPs and R_RISCV_ALIGN relocation

llvm/test/MC/RISCV/compress-rv32d.s

@@ -8,15 +8,15 @@
 # RUN: llvm-mc -triple riscv32 -mattr=+c,+d -filetype=obj < %s \
 # RUN:   | llvm-objdump  --triple=riscv32 --mattr=+c,+d -d -M no-aliases - \
 # RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcd,+d -show-encoding < %s \
+# RUN: llvm-mc -triple riscv32 -mattr=+zcd,+d -show-encoding < %s \
 # RUN:   | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcd,+d -show-encoding \
+# RUN: llvm-mc -triple riscv32 -mattr=+zcd,+d -show-encoding \
 # RUN:   -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcd,+d -filetype=obj < %s \
-# RUN:   | llvm-objdump  --triple=riscv32 --mattr=+experimental-zcd,+d -d - \
+# RUN: llvm-mc -triple riscv32 -mattr=+zcd,+d -filetype=obj < %s \
+# RUN:   | llvm-objdump  --triple=riscv32 --mattr=+zcd,+d -d - \
 # RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcd,+d -filetype=obj < %s \
-# RUN:   | llvm-objdump  --triple=riscv32 --mattr=+experimental-zcd,+d -d -M no-aliases - \
+# RUN: llvm-mc -triple riscv32 -mattr=+zcd,+d -filetype=obj < %s \
+# RUN:   | llvm-objdump  --triple=riscv32 --mattr=+zcd,+d -d -M no-aliases - \
 # RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
 # RUN: llvm-mc -triple riscv64 -mattr=+c,+d -show-encoding < %s \
@@ -29,15 +29,15 @@
 # RUN: llvm-mc -triple riscv64 -mattr=+c,+d -filetype=obj < %s \
 # RUN:   | llvm-objdump  --triple=riscv64 --mattr=+c,+d -d -M no-aliases - \
 # RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -mattr=+experimental-zcd,+d -show-encoding < %s \
+# RUN: llvm-mc -triple riscv64 -mattr=+zcd,+d -show-encoding < %s \
 # RUN:   | FileCheck -check-prefixes=CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -mattr=+experimental-zcd,+d -show-encoding \
+# RUN: llvm-mc -triple riscv64 -mattr=+zcd,+d -show-encoding \
 # RUN:   -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -mattr=+experimental-zcd,+d -filetype=obj < %s \
-# RUN:   | llvm-objdump  --triple=riscv64 --mattr=+experimental-zcd,+d -d - \
+# RUN: llvm-mc -triple riscv64 -mattr=+zcd,+d -filetype=obj < %s \
+# RUN:   | llvm-objdump  --triple=riscv64 --mattr=+zcd,+d -d - \
 # RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -mattr=+experimental-zcd,+d -filetype=obj < %s \
-# RUN:   | llvm-objdump  --triple=riscv64 --mattr=+experimental-zcd,+d -d -M no-aliases - \
+# RUN: llvm-mc -triple riscv64 -mattr=+zcd,+d -filetype=obj < %s \
+# RUN:   | llvm-objdump  --triple=riscv64 --mattr=+zcd,+d -d -M no-aliases - \
 # RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
 # Tests double precision floating point instructions available in rv32 and in rv64.

llvm/test/MC/RISCV/compress-rv32f.s

@@ -8,15 +8,15 @@
 # RUN: llvm-mc -triple riscv32 -mattr=+c,+f -filetype=obj < %s \
 # RUN:   | llvm-objdump  --triple=riscv32 --mattr=+c,+f -d -M no-aliases - \
 # RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcf,+f -show-encoding < %s \
+# RUN: llvm-mc -triple riscv32 -mattr=+zcf,+f -show-encoding < %s \
 # RUN:   | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcf,+f -show-encoding \
+# RUN: llvm-mc -triple riscv32 -mattr=+zcf,+f -show-encoding \
 # RUN:   -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcf,+f -filetype=obj < %s \
-# RUN:   | llvm-objdump  --triple=riscv32 --mattr=+experimental-zcf,+f -d - \
+# RUN: llvm-mc -triple riscv32 -mattr=+zcf,+f -filetype=obj < %s \
+# RUN:   | llvm-objdump  --triple=riscv32 --mattr=+zcf,+f -d - \
 # RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcf,+f -filetype=obj < %s \
-# RUN:   | llvm-objdump  --triple=riscv32 --mattr=+experimental-zcf,+f -d -M no-aliases - \
+# RUN: llvm-mc -triple riscv32 -mattr=+zcf,+f -filetype=obj < %s \
+# RUN:   | llvm-objdump  --triple=riscv32 --mattr=+zcf,+f -d -M no-aliases - \
 # RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
 # Instructions that are 32 bit only.