Revert "[RISCV] implement li pseudo instruction"

Reverts rL330224, while issues with the C extension and missed common
subexpression elimination opportunities are addressed. Neither of these issues
are visible in current RISC-V backend unit tests, which clearly need
expanding.

llvm-svn: 330281

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -9,7 +9,6 @@
 
 #include "MCTargetDesc/RISCVBaseInfo.h"
 #include "MCTargetDesc/RISCVMCExpr.h"
-#include "MCTargetDesc/RISCVMCPseudoExpansion.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringSwitch.h"
@@ -23,11 +22,8 @@
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/Casting.h"
-#include "llvm/Support/MathExtras.h"
 #include "llvm/Support/TargetRegistry.h"
 
-#include <limits>
-
 using namespace llvm;
 
 // Include the auto-generated portion of the compress emitter.
@@ -45,7 +41,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
                                       unsigned Kind) override;
 
   bool generateImmOutOfRangeError(OperandVector &Operands, uint64_t ErrorInfo,
-                                  int64_t Lower, int64_t Upper, Twine Msg);
+                                  int Lower, int Upper, Twine Msg);
 
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
@@ -59,12 +55,6 @@ class RISCVAsmParser : public MCTargetAsmParser {
 
   bool ParseDirective(AsmToken DirectiveID) override;
 
-  /// Helper for emitting MC instructions that have been successfully matched
-  /// by MatchAndEmitInstruction. Modifications to the emitted instructions,
-  /// like the expansion of pseudo instructions (e.g., "li"), can be performed
-  /// in this method.
-  bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
-
 // Auto-generated instruction matching functions
 #define GET_ASSEMBLER_HEADER
 #include "RISCVGenAsmMatcher.inc"
@@ -220,18 +210,6 @@ struct RISCVOperand : public MCParsedAsmOperand {
     return RISCVFPRndMode::stringToRoundingMode(Str) != RISCVFPRndMode::Invalid;
   }
 
-  bool isImmXLen() const {
-    int64_t Imm;
-    RISCVMCExpr::VariantKind VK;
-    if (!isImm())
-      return false;
-    bool IsConstantImm = evaluateConstantImm(Imm, VK);
-    // Given only Imm, ensuring that the actually specified constant is either
-    // a signed or unsigned 64-bit number is unfortunately impossible.
-    bool IsInRange = isRV64() ? true : isInt<32>(Imm) || isUInt<32>(Imm);
-    return IsConstantImm && IsInRange && VK == RISCVMCExpr::VK_RISCV_None;
-  }
-
   bool isUImmLog2XLen() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK;
@@ -605,7 +583,7 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
 }
 
 bool RISCVAsmParser::generateImmOutOfRangeError(
-    OperandVector &Operands, uint64_t ErrorInfo, int64_t Lower, int64_t Upper,
+    OperandVector &Operands, uint64_t ErrorInfo, int Lower, int Upper,
     Twine Msg = "immediate must be an integer in the range") {
   SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
   return Error(ErrorLoc, Msg + " [" + Twine(Lower) + ", " + Twine(Upper) + "]");
@@ -621,8 +599,14 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
   default:
     break;
-  case Match_Success:
-    return processInstruction(Inst, IDLoc, Out);
+  case Match_Success: {
+    MCInst CInst;
+    bool Res = compressInst(CInst, Inst, getSTI(), Out.getContext());
+    CInst.setLoc(IDLoc);
+    Inst.setLoc(IDLoc);
+    Out.EmitInstruction((Res ? CInst : Inst), getSTI());
+    return false;
+  }
   case Match_MissingFeature:
     return Error(IDLoc, "instruction use requires an option to be enabled");
   case Match_MnemonicFail:
@@ -639,14 +623,6 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
     }
     return Error(ErrorLoc, "invalid operand for instruction");
   }
-  case Match_InvalidImmXLen:
-    if (isRV64()) {
-      SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
-      return Error(ErrorLoc, "operand must be a constant 64-bit integer");
-    }
-    return generateImmOutOfRangeError(Operands, ErrorInfo,
-                                      std::numeric_limits<int32_t>::min(),
-                                      std::numeric_limits<uint32_t>::max());
   case Match_InvalidUImmLog2XLen:
     if (isRV64())
       return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1);
@@ -991,31 +967,6 @@ bool RISCVAsmParser::classifySymbolRef(const MCExpr *Expr,
   return Kind != RISCVMCExpr::VK_RISCV_Invalid;
 }
 
-bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
-                                        MCStreamer &Out) {
-  Inst.setLoc(IDLoc);
-
-  switch (Inst.getOpcode()) {
-  case RISCV::PseudoLI: {
-    auto Reg = Inst.getOperand(0).getReg();
-    int64_t Imm = Inst.getOperand(1).getImm();
-    // On RV32 the immediate here can either be a signed or an unsigned
-    // 32-bit number. Sign extension has to be performed to ensure that Imm
-    // represents the expected signed 64-bit number.
-    if (!isRV64())
-      Imm = SignExtend64<32>(Imm);
-    emitRISCVLoadImm(Reg, Imm, Out, STI);
-    return false;
-  }
-  }
-
-  MCInst CInst;
-  bool Res = compressInst(CInst, Inst, getSTI(), Out.getContext());
-  CInst.setLoc(IDLoc);
-  Out.EmitInstruction((Res ? CInst : Inst), getSTI());
-  return false;
-}
-
 bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID) { return true; }
 
 extern "C" void LLVMInitializeRISCVAsmParser() {

llvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt

@@ -4,7 +4,6 @@ add_llvm_library(LLVMRISCVDesc
   RISCVMCAsmInfo.cpp
   RISCVMCCodeEmitter.cpp
   RISCVMCExpr.cpp
-  RISCVMCPseudoExpansion.cpp
   RISCVMCTargetDesc.cpp
   RISCVTargetStreamer.cpp
   RISCVELFStreamer.cpp

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

@@ -15,7 +15,6 @@
 #include "RISCV.h"
 #include "InstPrinter/RISCVInstPrinter.h"
 #include "MCTargetDesc/RISCVMCExpr.h"
-#include "MCTargetDesc/RISCVMCPseudoExpansion.h"
 #include "RISCVTargetMachine.h"
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
@@ -79,14 +78,6 @@ void RISCVAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   if (emitPseudoExpansionLowering(*OutStreamer, MI))
     return;
 
-  if (MI->getOpcode() == RISCV::PseudoLI) {
-    const MachineOperand &DstRegOp = MI->getOperand(0);
-    const MachineOperand &ImmOp = MI->getOperand(1);
-    emitRISCVLoadImm(DstRegOp.getReg(), ImmOp.getImm(), *OutStreamer,
-                     &getSubtargetInfo());
-    return;
-  }
-
   MCInst TmpInst;
   LowerRISCVMachineInstrToMCInst(MI, TmpInst, *this);
   EmitToStreamer(*OutStreamer, TmpInst);

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -179,62 +179,41 @@ void RISCVDAGToDAGISel::doPeepholeLoadStoreADDI() {
 
     SDValue Base = N->getOperand(BaseOpIdx);
 
-    // If the base is an ADDI or PseudoLI, we can either merge it or at least
-    // sink the lowest 12 bits into the load/store.
-    if (!Base.isMachineOpcode() || (Base.getMachineOpcode() != RISCV::ADDI &&
-                                    Base.getMachineOpcode() != RISCV::PseudoLI))
+    // If the base is an ADDI, we can merge it in to the load/store.
+    if (!Base.isMachineOpcode() || Base.getMachineOpcode() != RISCV::ADDI)
       continue;
 
-    SDValue ImmOperand;
-    SDValue Parent;
-    if (Base.getMachineOpcode() == RISCV::PseudoLI) {
-      ImmOperand = Base.getOperand(0);
-      auto Const = dyn_cast<ConstantSDNode>(ImmOperand);
-      if (!Const || (Const->getSExtValue() & 0xFFF) == 0)
-        continue;
-
-      int64_t Hi52 = (Const->getSExtValue() + 0x800) & ~0xFFF;
-      SDValue HiVal = CurDAG->getTargetConstant(Hi52, SDLoc(ImmOperand),
-                                                ImmOperand.getValueType());
-      Parent =
-          SDValue(CurDAG->getMachineNode(RISCV::PseudoLI, SDLoc(ImmOperand),
-                                         ImmOperand.getValueType(), HiVal),
-                  0);
-
-      int64_t Lo12 = SignExtend64<12>(Const->getSExtValue());
-      ImmOperand = CurDAG->getTargetConstant(Lo12, SDLoc(ImmOperand),
-                                             ImmOperand.getValueType());
+    SDValue ImmOperand = Base.getOperand(1);
+
+    if (auto Const = dyn_cast<ConstantSDNode>(ImmOperand)) {
+      ImmOperand = CurDAG->getTargetConstant(
+          Const->getSExtValue(), SDLoc(ImmOperand), ImmOperand.getValueType());
+    } else if (auto GA = dyn_cast<GlobalAddressSDNode>(ImmOperand)) {
+      ImmOperand = CurDAG->getTargetGlobalAddress(
+          GA->getGlobal(), SDLoc(ImmOperand), ImmOperand.getValueType(),
+          GA->getOffset(), GA->getTargetFlags());
     } else {
-      Parent = Base.getOperand(0);
-      ImmOperand = Base.getOperand(1);
-
-      if (auto Const = dyn_cast<ConstantSDNode>(ImmOperand)) {
-        ImmOperand =
-            CurDAG->getTargetConstant(Const->getSExtValue(), SDLoc(ImmOperand),
-                                      ImmOperand.getValueType());
-      } else if (auto GA = dyn_cast<GlobalAddressSDNode>(ImmOperand)) {
-        ImmOperand = CurDAG->getTargetGlobalAddress(
-            GA->getGlobal(), SDLoc(ImmOperand), ImmOperand.getValueType(),
-            GA->getOffset(), GA->getTargetFlags());
-      } else {
-        continue;
-      }
+      continue;
     }
 
-    DEBUG(dbgs() << "Folding add-immediate or PseudoLI into mem-op:\nBase: ");
-    DEBUG(Base.dump(CurDAG));
+    DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase:    ");
+    DEBUG(Base->dump(CurDAG));
     DEBUG(dbgs() << "\nN: ");
     DEBUG(N->dump(CurDAG));
     DEBUG(dbgs() << "\n");
 
     // Modify the offset operand of the load/store.
     if (BaseOpIdx == 0) // Load
-      CurDAG->UpdateNodeOperands(N, Parent, ImmOperand, N->getOperand(2));
+      CurDAG->UpdateNodeOperands(N, Base.getOperand(0), ImmOperand,
+                                 N->getOperand(2));
     else // Store
-      CurDAG->UpdateNodeOperands(N, N->getOperand(0), Parent, ImmOperand,
-                                 N->getOperand(3));
+      CurDAG->UpdateNodeOperands(N, N->getOperand(0), Base.getOperand(0),
+                                 ImmOperand, N->getOperand(3));
+
+    // The add-immediate may now be dead, in which case remove it.
+    if (Base.getNode()->use_empty())
+      CurDAG->RemoveDeadNode(Base.getNode());
   }
-  CurDAG->RemoveDeadNodes();
 }
 
 // Remove redundant BuildPairF64+SplitF64 pairs. i.e. cases where an f64 is

llvm/lib/Target/RISCV/RISCVInstrFormats.td

@@ -102,8 +102,8 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
 }
 
 // Pseudo instructions
-class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">
-    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo> {
+class Pseudo<dag outs, dag ins, list<dag> pattern>
+    : RVInst<outs, ins, "", "", pattern, InstFormatPseudo> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }