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[GlobalISel][X86] Support G_LSHR/G_ASHR/G_SHL
Support G_LSHR/G_ASHR/G_SHL. We have 3 variance for shift instructions : shift gpr, shift imm, shift 1. Currently GlobalIsel TableGen generate patterns for shift imm and shift 1, but with shiftCount i8. In G_LSHR/G_ASHR/G_SHL like LLVM-IR both arguments has the same type, so for now only shift i8 can use auto generated TableGen patterns. The support of G_SHL/G_ASHR enables tryCombineSExt from LegalizationArtifactCombiner.h to hit, which results in different legalization for the following tests: LLVM :: CodeGen/X86/GlobalISel/ext-x86-64.ll LLVM :: CodeGen/X86/GlobalISel/gep.ll LLVM :: CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir -; X64-NEXT: movsbl %dil, %eax +; X64-NEXT: movl $24, %ecx +; X64-NEXT: # kill: def $cl killed $ecx +; X64-NEXT: shll %cl, %edi +; X64-NEXT: movl $24, %ecx +; X64-NEXT: # kill: def $cl killed $ecx +; X64-NEXT: sarl %cl, %edi +; X64-NEXT: movl %edi, %eax ..which is not optimal and should be addressed later. Rework of the patch by igorb Reviewed By: igorb Differential Revision: https://reviews.llvm.org/D44395 llvm-svn: 327499
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Alexander Ivchenko
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Mar 14, 2018
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | ||
; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X64 | ||
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define i64 @test_ashr_i64(i64 %arg1, i64 %arg2) { | ||
; X64-LABEL: test_ashr_i64: | ||
; X64: # %bb.0: | ||
; X64-NEXT: movq %rsi, %rcx | ||
; X64-NEXT: # kill: def $cl killed $rcx | ||
; X64-NEXT: sarq %cl, %rdi | ||
; X64-NEXT: movq %rdi, %rax | ||
; X64-NEXT: retq | ||
%res = ashr i64 %arg1, %arg2 | ||
ret i64 %res | ||
} | ||
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define i64 @test_ashr_i64_imm(i64 %arg1) { | ||
; X64-LABEL: test_ashr_i64_imm: | ||
; X64: # %bb.0: | ||
; X64-NEXT: movq $5, %rcx | ||
; X64-NEXT: # kill: def $cl killed $rcx | ||
; X64-NEXT: sarq %cl, %rdi | ||
; X64-NEXT: movq %rdi, %rax | ||
; X64-NEXT: retq | ||
%res = ashr i64 %arg1, 5 | ||
ret i64 %res | ||
} | ||
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define i64 @test_ashr_i64_imm1(i64 %arg1) { | ||
; X64-LABEL: test_ashr_i64_imm1: | ||
; X64: # %bb.0: | ||
; X64-NEXT: movq $1, %rcx | ||
; X64-NEXT: # kill: def $cl killed $rcx | ||
; X64-NEXT: sarq %cl, %rdi | ||
; X64-NEXT: movq %rdi, %rax | ||
; X64-NEXT: retq | ||
%res = ashr i64 %arg1, 1 | ||
ret i64 %res | ||
} | ||
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define i32 @test_ashr_i32(i32 %arg1, i32 %arg2) { | ||
; X64-LABEL: test_ashr_i32: | ||
; X64: # %bb.0: | ||
; X64-NEXT: movl %esi, %ecx | ||
; X64-NEXT: # kill: def $cl killed $ecx | ||
; X64-NEXT: sarl %cl, %edi | ||
; X64-NEXT: movl %edi, %eax | ||
; X64-NEXT: retq | ||
%res = ashr i32 %arg1, %arg2 | ||
ret i32 %res | ||
} | ||
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define i32 @test_ashr_i32_imm(i32 %arg1) { | ||
; X64-LABEL: test_ashr_i32_imm: | ||
; X64: # %bb.0: | ||
; X64-NEXT: movl $5, %ecx | ||
; X64-NEXT: # kill: def $cl killed $ecx | ||
; X64-NEXT: sarl %cl, %edi | ||
; X64-NEXT: movl %edi, %eax | ||
; X64-NEXT: retq | ||
%res = ashr i32 %arg1, 5 | ||
ret i32 %res | ||
} | ||
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define i32 @test_ashr_i32_imm1(i32 %arg1) { | ||
; X64-LABEL: test_ashr_i32_imm1: | ||
; X64: # %bb.0: | ||
; X64-NEXT: movl $1, %ecx | ||
; X64-NEXT: # kill: def $cl killed $ecx | ||
; X64-NEXT: sarl %cl, %edi | ||
; X64-NEXT: movl %edi, %eax | ||
; X64-NEXT: retq | ||
%res = ashr i32 %arg1, 1 | ||
ret i32 %res | ||
} | ||
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define i16 @test_ashr_i16(i32 %arg1, i32 %arg2) { | ||
; X64-LABEL: test_ashr_i16: | ||
; X64: # %bb.0: | ||
; X64-NEXT: movl %esi, %ecx | ||
; X64-NEXT: # kill: def $cl killed $cx | ||
; X64-NEXT: sarw %cl, %di | ||
; X64-NEXT: movl %edi, %eax | ||
; X64-NEXT: retq | ||
%a = trunc i32 %arg1 to i16 | ||
%a2 = trunc i32 %arg2 to i16 | ||
%res = ashr i16 %a, %a2 | ||
ret i16 %res | ||
} | ||
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define i16 @test_ashr_i16_imm(i32 %arg1) { | ||
; X64-LABEL: test_ashr_i16_imm: | ||
; X64: # %bb.0: | ||
; X64-NEXT: movw $5, %cx | ||
; X64-NEXT: # kill: def $cl killed $cx | ||
; X64-NEXT: sarw %cl, %di | ||
; X64-NEXT: movl %edi, %eax | ||
; X64-NEXT: retq | ||
%a = trunc i32 %arg1 to i16 | ||
%res = ashr i16 %a, 5 | ||
ret i16 %res | ||
} | ||
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define i16 @test_ashr_i16_imm1(i32 %arg1) { | ||
; X64-LABEL: test_ashr_i16_imm1: | ||
; X64: # %bb.0: | ||
; X64-NEXT: movw $1, %cx | ||
; X64-NEXT: # kill: def $cl killed $cx | ||
; X64-NEXT: sarw %cl, %di | ||
; X64-NEXT: movl %edi, %eax | ||
; X64-NEXT: retq | ||
%a = trunc i32 %arg1 to i16 | ||
%res = ashr i16 %a, 1 | ||
ret i16 %res | ||
} | ||
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define i8 @test_ashr_i8(i32 %arg1, i32 %arg2) { | ||
; X64-LABEL: test_ashr_i8: | ||
; X64: # %bb.0: | ||
; X64-NEXT: movl %esi, %ecx | ||
; X64-NEXT: sarb %cl, %dil | ||
; X64-NEXT: movl %edi, %eax | ||
; X64-NEXT: retq | ||
%a = trunc i32 %arg1 to i8 | ||
%a2 = trunc i32 %arg2 to i8 | ||
%res = ashr i8 %a, %a2 | ||
ret i8 %res | ||
} | ||
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define i8 @test_ashr_i8_imm(i32 %arg1) { | ||
; X64-LABEL: test_ashr_i8_imm: | ||
; X64: # %bb.0: | ||
; X64-NEXT: sarb $5, %dil | ||
; X64-NEXT: movl %edi, %eax | ||
; X64-NEXT: retq | ||
%a = trunc i32 %arg1 to i8 | ||
%res = ashr i8 %a, 5 | ||
ret i8 %res | ||
} | ||
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define i8 @test_ashr_i8_imm1(i32 %arg1) { | ||
; X64-LABEL: test_ashr_i8_imm1: | ||
; X64: # %bb.0: | ||
; X64-NEXT: sarb %dil | ||
; X64-NEXT: movl %edi, %eax | ||
; X64-NEXT: retq | ||
%a = trunc i32 %arg1 to i8 | ||
%res = ashr i8 %a, 1 | ||
ret i8 %res | ||
} | ||
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define i1 @test_ashr_i1(i32 %arg1, i32 %arg2) { | ||
; X64-LABEL: test_ashr_i1: | ||
; X64: # %bb.0: | ||
; X64-NEXT: shlb $7, %dil | ||
; X64-NEXT: sarb $7, %dil | ||
; X64-NEXT: shlb $7, %sil | ||
; X64-NEXT: sarb $7, %sil | ||
; X64-NEXT: movl %esi, %ecx | ||
; X64-NEXT: sarb %cl, %dil | ||
; X64-NEXT: movl %edi, %eax | ||
; X64-NEXT: retq | ||
%a = trunc i32 %arg1 to i1 | ||
%a2 = trunc i32 %arg2 to i1 | ||
%res = ashr i1 %a, %a2 | ||
ret i1 %res | ||
} | ||
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define i1 @test_ashr_i1_imm1(i32 %arg1) { | ||
; X64-LABEL: test_ashr_i1_imm1: | ||
; X64: # %bb.0: | ||
; X64-NEXT: movb $-1, %cl | ||
; X64-NEXT: shlb $7, %dil | ||
; X64-NEXT: sarb $7, %dil | ||
; X64-NEXT: shlb $7, %cl | ||
; X64-NEXT: sarb $7, %cl | ||
; X64-NEXT: sarb %cl, %dil | ||
; X64-NEXT: movl %edi, %eax | ||
; X64-NEXT: retq | ||
%a = trunc i32 %arg1 to i1 | ||
%res = ashr i1 %a, 1 | ||
ret i1 %res | ||
} |
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