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[mips] Honour -mno-odd-spreg for vector splat (again)
Previous the lowering of FILL_FW would use the MSA128W register class when performing a vector splat. Instead it should be honouring -mno-odd-spreg and only use the even registers when performing a splat from word to vector register. Logical follow-on from r230235. This fixes PR/31369. A previous commit was missing the test case and had another differential in it. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D28373 llvm-svn: 291566
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Simon Dardis
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Jan 10, 2017
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; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg < %s | FileCheck %s | ||
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; Test that the register allocator honours +nooddspreg and does not pick an odd | ||
; single precision subregister of an MSA register. | ||
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@f1 = external global float | ||
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@f2 = external global float | ||
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@v3 = external global <4 x float> | ||
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@d1 = external global double | ||
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define void @test() { | ||
; CHECK-LABEL: test: | ||
entry: | ||
; CHECK-NOT: lwc1 $f{{[13579]+}} | ||
; CHECK: lwc1 $f{{[02468]+}} | ||
%0 = load float, float * @f1 | ||
%1 = insertelement <4 x float> undef, float %0, i32 0 | ||
%2 = insertelement <4 x float> %1, float %0, i32 1 | ||
%3 = insertelement <4 x float> %2, float %0, i32 2 | ||
%4 = insertelement <4 x float> %3, float %0, i32 3 | ||
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; CHECK-NOT: lwc1 $f{{[13579]+}} | ||
; CHECK: lwc1 $f{{[02468]+}} | ||
%5 = load float, float * @f2 | ||
%6 = insertelement <4 x float> undef, float %5, i32 0 | ||
%7 = insertelement <4 x float> %6, float %5, i32 1 | ||
%8 = insertelement <4 x float> %7, float %5, i32 2 | ||
%9 = insertelement <4 x float> %8, float %5, i32 3 | ||
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%10 = fadd <4 x float> %4, %9 | ||
store <4 x float> %10, <4 x float> * @v3 | ||
ret void | ||
} | ||
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; Test that the register allocator hnours +noodspreg and does not pick an odd | ||
; single precision register for a load to perform a conversion to a double. | ||
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define void @test2() { | ||
; CHECK-LABEL: test2: | ||
entry: | ||
; CHECK-NOT: lwc1 $f{{[13579]+}} | ||
; CHECK: lwc1 $f{{[02468]+}} | ||
%0 = load float, float * @f1 | ||
%1 = fpext float %0 to double | ||
; CHECK-NOT: lwc1 $f{{[13579]+}} | ||
; CHECK: lwc1 $f{{[02468]+}} | ||
%2 = load float, float * @f2 | ||
%3 = fpext float %2 to double | ||
%4 = fadd double %1, %3 | ||
store double%4, double * @d1 | ||
ret void | ||
} |