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[AArch64] Enable merging of adjacent zero stores for all subtargets.
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This optimization merges adjacent zero stores into a wider store.

e.g.,

strh wzr, [x0]
strh wzr, [x0, #2]
; becomes
str wzr, [x0]

e.g.,

str wzr, [x0]
str wzr, [x0, #4]
; becomes
str xzr, [x0]

Previously, this was only enabled for Kryo and Cortex-A57.

Differential Revision: https://reviews.llvm.org/D26396

llvm-svn: 286592
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Chad Rosier committed Nov 11, 2016
1 parent ce0aba7 commit 10c7aaa
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Showing 4 changed files with 2 additions and 14 deletions.
7 changes: 0 additions & 7 deletions llvm/lib/Target/AArch64/AArch64.td
Expand Up @@ -61,11 +61,6 @@ def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
"Reserve X18, making it unavailable "
"as a GPR">;

def FeatureMergeNarrowZeroSt : SubtargetFeature<"merge-narrow-zero-st",
"MergeNarrowZeroStores", "true",
"Merge narrow zero store "
"instructions">;

def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
"Use alias analysis during codegen">;

Expand Down Expand Up @@ -182,7 +177,6 @@ def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
FeatureCrypto,
FeatureCustomCheapAsMoveHandling,
FeatureFPARMv8,
FeatureMergeNarrowZeroSt,
FeatureNEON,
FeaturePerfMon,
FeaturePostRAScheduler,
Expand Down Expand Up @@ -253,7 +247,6 @@ def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
FeatureCrypto,
FeatureCustomCheapAsMoveHandling,
FeatureFPARMv8,
FeatureMergeNarrowZeroSt,
FeatureNEON,
FeaturePerfMon,
FeaturePostRAScheduler,
Expand Down
3 changes: 1 addition & 2 deletions llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
Expand Up @@ -1699,8 +1699,7 @@ bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
UsedRegs.resize(TRI->getNumRegs());

bool Modified = false;
bool enableNarrowZeroStOpt =
Subtarget->mergeNarrowStores() && !Subtarget->requiresStrictAlign();
bool enableNarrowZeroStOpt = !Subtarget->requiresStrictAlign();
for (auto &MBB : Fn)
Modified |= optimizeBlock(MBB, enableNarrowZeroStOpt);

Expand Down
2 changes: 0 additions & 2 deletions llvm/lib/Target/AArch64/AArch64Subtarget.h
Expand Up @@ -71,7 +71,6 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {

// StrictAlign - Disallow unaligned memory accesses.
bool StrictAlign = false;
bool MergeNarrowZeroStores = false;
bool UseAA = false;
bool PredictableSelectIsExpensive = false;
bool BalanceFPOps = false;
Expand Down Expand Up @@ -179,7 +178,6 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
bool hasCrypto() const { return HasCrypto; }
bool hasCRC() const { return HasCRC; }
bool hasRAS() const { return HasRAS; }
bool mergeNarrowStores() const { return MergeNarrowZeroStores; }
bool balanceFPOps() const { return BalanceFPOps; }
bool predictableSelectIsExpensive() const {
return PredictableSelectIsExpensive;
Expand Down
4 changes: 1 addition & 3 deletions llvm/test/CodeGen/AArch64/arm64-narrow-st-merge.ll
@@ -1,6 +1,4 @@
; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=cortex-a57 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple aarch64_be--none-eabi -mcpu=cortex-a57 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=kryo -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple aarch64--none-eabi -verify-machineinstrs | FileCheck %s

; CHECK-LABEL: Strh_zero
; CHECK: str wzr
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