[AMDGPU][DOC][NFC] Added GFX1013 assembler syntax description

llvm · Apr 1, 2022 · 111cb39 · 111cb39
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diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX1013.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX1013.rst
@@ -0,0 +1,57 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+====================================================================================
+Syntax of gfx1013 Instructions
+====================================================================================
+
+.. contents::
+  :local:
+
+Introduction
+============
+
+This document describes the syntax of *instructions specific to gfx1013*.
+
+For a description of other gfx1013 instructions see :doc:`Syntax of GFX10 RDNA1 Instructions<AMDGPUAsmGFX10>`.
+
+Notation
+========
+
+Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
+
+Overview
+========
+
+An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
+
+Instructions
+============
+
+
+MIMG
+----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                   **DST**      **SRC0**     **SRC1**       **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    image_bvh64_intersect_ray     :ref:`vdst<amdgpu_synid_gfx1013_vdst_f8490d>`,    :ref:`vaddr<amdgpu_synid_gfx1013_vaddr_49d53a>`,   :ref:`srsrc<amdgpu_synid_gfx1013_srsrc_5dafbc>`      :ref:`a16<amdgpu_synid_a16>`
+    image_bvh_intersect_ray       :ref:`vdst<amdgpu_synid_gfx1013_vdst_f8490d>`,    :ref:`vaddr<amdgpu_synid_gfx1013_vaddr_49d53a>`,   :ref:`srsrc<amdgpu_synid_gfx1013_srsrc_5dafbc>`      :ref:`a16<amdgpu_synid_a16>`
+    image_msaa_load               :ref:`vdst<amdgpu_synid_gfx1013_vdst_473a69>`,    :ref:`vaddr<amdgpu_synid_gfx1013_vaddr_cdc744>`,   :ref:`srsrc<amdgpu_synid_gfx1013_srsrc_cf7132>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+
+.. |---| unicode:: U+02014 .. em dash
+
+.. toctree::
+    :hidden:
+
+    gfx1013_srsrc_5dafbc
+    gfx1013_srsrc_cf7132
+    gfx1013_vaddr_49d53a
+    gfx1013_vaddr_cdc744
+    gfx1013_vdst_473a69
+    gfx1013_vdst_f8490d
diff --git a/llvm/docs/AMDGPU/gfx1013_srsrc_5dafbc.rst b/llvm/docs/AMDGPU/gfx1013_srsrc_5dafbc.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx1013_srsrc_5dafbc:
+
+srsrc
+=====
+
+Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx1013_srsrc_cf7132.rst b/llvm/docs/AMDGPU/gfx1013_srsrc_cf7132.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx1013_srsrc_cf7132:
+
+srsrc
+=====
+
+Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
+
+*Size:* 8 dwords by default, 4 dwords if :ref:`r128<amdgpu_synid_r128>` is specified.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx1013_vaddr_49d53a.rst b/llvm/docs/AMDGPU/gfx1013_vaddr_49d53a.rst
@@ -0,0 +1,29 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx1013_vaddr_49d53a:
+
+vaddr
+=====
+
+Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
+
+This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
+
+*Size:* 8-12 dwords. Actual size depends on :ref:`a16<amdgpu_synid_a16>`.
+
+* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 8-12 dwords.
+* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 8 dwords. Opcodes which require more than 8 dwords for address size must specify 16 dwords due to a limited range of supported register sequences.
+
+  Examples:
+
+  .. parsed-literal::
+
+    image_bvh_intersect_ray v[4:7], v[9:24], s[4:7]
+    image_bvh_intersect_ray v[39:42], [v5, v4, v2, v1, v7, v3, v0, v6], s[12:15] a16
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1013_vaddr_cdc744.rst b/llvm/docs/AMDGPU/gfx1013_vaddr_cdc744.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx1013_vaddr_cdc744:
+
+vaddr
+=====
+
+Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
+
+This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
+
+*Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
+
+* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
+* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1-8 dwords. Opcodes which require more than 8 dwords for address size must specify 16 dwords due to a limited range of supported register sequences.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1013_vdst_473a69.rst b/llvm/docs/AMDGPU/gfx1013_vdst_473a69.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx1013_vdst_473a69:
+
+vdst
+====
+
+Image data to load by an image instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`, :ref:`tfe<amdgpu_synid_tfe>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1013_vdst_f8490d.rst b/llvm/docs/AMDGPU/gfx1013_vdst_f8490d.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx1013_vdst_f8490d:
+
+vdst
+====
+
+Image data to load by an image instruction.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
@@ -18,6 +18,7 @@ User Guide for AMDGPU Backend
    AMDGPU/AMDGPUAsmGFX90a
    AMDGPU/AMDGPUAsmGFX10
    AMDGPU/AMDGPUAsmGFX1011
+   AMDGPU/AMDGPUAsmGFX1013
    AMDGPU/AMDGPUAsmGFX1030
    AMDGPUModifierSyntax
    AMDGPUOperandSyntax
@@ -14204,6 +14205,8 @@ in this description.
 
                                                                 :doc:`gfx1012<AMDGPU/AMDGPUAsmGFX1011>`
 
+                                                                :doc:`gfx1013<AMDGPU/AMDGPUAsmGFX1013>`
+
     RDNA 2        :doc:`GFX10 RDNA2<AMDGPU/AMDGPUAsmGFX1030>`   :doc:`gfx1030<AMDGPU/AMDGPUAsmGFX1030>`
 
                                                                 :doc:`gfx1031<AMDGPU/AMDGPUAsmGFX1030>`