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[CodeGen] Rename MachineInstrBuilder::addOperand. NFC
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Rename from addOperand to just add, to match the other method that has been
added to MachineInstrBuilder for adding more than just 1 operand.

See https://reviews.llvm.org/D28057 for the whole discussion.

Differential Revision: https://reviews.llvm.org/D28556

llvm-svn: 291891
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@rovka
rovka committed Jan 13, 2017
1 parent 4f8c3e1 commit 116bbab
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Showing 66 changed files with 604 additions and 608 deletions.
2 changes: 1 addition & 1 deletion llvm/include/llvm/CodeGen/MachineInstrBuilder.h
View file
Expand Up @@ -187,7 +187,7 @@ class MachineInstrBuilder {
return *this;
}

const MachineInstrBuilder &addOperand(const MachineOperand &MO) const {
const MachineInstrBuilder &add(const MachineOperand &MO) const {
MI->addOperand(*MF, MO);
return *this;
}
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/ImplicitNullChecks.cpp
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Expand Up @@ -522,7 +522,7 @@ ImplicitNullChecks::insertFaultingLoad(MachineInstr *LoadMI,
.addImm(LoadMI->getOpcode());

for (auto &MO : LoadMI->uses())
MIB.addOperand(MO);
MIB.add(MO);

MIB.setMemRefs(LoadMI->memoperands_begin(), LoadMI->memoperands_end());

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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/LiveDebugVariables.cpp
View file
Expand Up @@ -944,7 +944,7 @@ void UserValue::insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx,
IsIndirect, Loc.getReg(), offset, Variable, Expression);
else
BuildMI(*MBB, I, getDebugLoc(), TII.get(TargetOpcode::DBG_VALUE))
.addOperand(Loc)
.add(Loc)
.addImm(offset)
.addMetadata(Variable)
.addMetadata(Expression);
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/PatchableFunction.cpp
View file
Expand Up @@ -75,7 +75,7 @@ bool PatchableFunction::runOnMachineFunction(MachineFunction &MF) {
.addImm(FirstActualI->getOpcode());

for (auto &MO : FirstActualI->operands())
MIB.addOperand(MO);
MIB.add(MO);

FirstActualI->eraseFromParent();
MF.ensureAlignment(4);
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6 changes: 3 additions & 3 deletions llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
View file
Expand Up @@ -646,7 +646,7 @@ bool FastISel::selectStackmap(const CallInst *I) {
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::STACKMAP));
for (auto const &MO : Ops)
MIB.addOperand(MO);
MIB.add(MO);

// Issue CALLSEQ_END
unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
Expand Down Expand Up @@ -826,7 +826,7 @@ bool FastISel::selectPatchpoint(const CallInst *I) {
TII.get(TargetOpcode::PATCHPOINT));

for (auto &MO : Ops)
MIB.addOperand(MO);
MIB.add(MO);

MIB->setPhysRegsDeadExcept(CLI.InRegs, TRI);

Expand Down Expand Up @@ -1149,7 +1149,7 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) {
} else
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::DBG_VALUE))
.addOperand(*Op)
.add(*Op)
.addImm(0)
.addMetadata(DI->getVariable())
.addMetadata(DI->getExpression());
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View file
Expand Up @@ -4752,7 +4752,7 @@ bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
else
FuncInfo.ArgDbgValues.push_back(
BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
.addOperand(*Op)
.add(*Op)
.addImm(Offset)
.addMetadata(Variable)
.addMetadata(Expr));
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4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/TargetInstrInfo.cpp
View file
Expand Up @@ -470,7 +470,7 @@ static MachineInstr *foldPatchpoint(MachineFunction &MF, MachineInstr &MI,

// No need to fold return, the meta data, and function arguments
for (unsigned i = 0; i < StartIdx; ++i)
MIB.addOperand(MI.getOperand(i));
MIB.add(MI.getOperand(i));

for (unsigned i = StartIdx; i < MI.getNumOperands(); ++i) {
MachineOperand &MO = MI.getOperand(i);
Expand All @@ -490,7 +490,7 @@ static MachineInstr *foldPatchpoint(MachineFunction &MF, MachineInstr &MI,
MIB.addImm(SpillOffset);
}
else
MIB.addOperand(MO);
MIB.add(MO);
}
return NewMI;
}
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8 changes: 4 additions & 4 deletions llvm/lib/CodeGen/TargetLoweringBase.cpp
View file
Expand Up @@ -1227,7 +1227,7 @@ TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,

// Copy operands before the frame-index.
for (unsigned i = 0; i < OperIdx; ++i)
MIB.addOperand(MI->getOperand(i));
MIB.add(MI->getOperand(i));
// Add frame index operands recognized by stackmaps.cpp
if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
// indirect-mem-ref tag, size, #FI, offset.
Expand All @@ -1237,18 +1237,18 @@ TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
MIB.addImm(StackMaps::IndirectMemRefOp);
MIB.addImm(MFI.getObjectSize(FI));
MIB.addOperand(MI->getOperand(OperIdx));
MIB.add(MI->getOperand(OperIdx));
MIB.addImm(0);
} else {
// direct-mem-ref tag, #FI, offset.
// Used by patchpoint, and direct alloca arguments to statepoints
MIB.addImm(StackMaps::DirectMemRefOp);
MIB.addOperand(MI->getOperand(OperIdx));
MIB.add(MI->getOperand(OperIdx));
MIB.addImm(0);
}
// Copy the operands after the frame index.
for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
MIB.addOperand(MI->getOperand(i));
MIB.add(MI->getOperand(i));

// Inherit previous memory operands.
MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
View file
Expand Up @@ -1785,7 +1785,7 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
MachineInstr *CopyMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
TII->get(TargetOpcode::COPY))
.addReg(DstReg, RegState::Define, SubIdx)
.addOperand(UseMO);
.add(UseMO);

// The first def needs an <undef> flag because there is no live register
// before it.
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/XRayInstrumentation.cpp
View file
Expand Up @@ -81,7 +81,7 @@ void XRayInstrumentation::replaceRetWithPatchableRet(MachineFunction &MF,
auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc))
.addImm(T.getOpcode());
for (auto &MO : T.operands())
MIB.addOperand(MO);
MIB.add(MO);
Terminators.push_back(&T);
}
}
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64CallLowering.cpp
View file
Expand Up @@ -264,7 +264,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
// uses of arg registers.
auto MIB = MIRBuilder.buildInstrNoInsert(Callee.isReg() ? AArch64::BLR
: AArch64::BL);
MIB.addOperand(Callee);
MIB.add(Callee);

// Tell the call which registers are clobbered.
auto TRI = MF.getSubtarget().getRegisterInfo();
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8 changes: 4 additions & 4 deletions llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
View file
Expand Up @@ -265,10 +265,10 @@ void AArch64ConditionOptimizer::modifyCmp(MachineInstr *CmpMI,

// Change immediate in comparison instruction (ADDS or SUBS).
BuildMI(*MBB, CmpMI, CmpMI->getDebugLoc(), TII->get(Opc))
.addOperand(CmpMI->getOperand(0))
.addOperand(CmpMI->getOperand(1))
.add(CmpMI->getOperand(0))
.add(CmpMI->getOperand(1))
.addImm(Imm)
.addOperand(CmpMI->getOperand(3));
.add(CmpMI->getOperand(3));
CmpMI->eraseFromParent();

// The fact that this comparison was picked ensures that it's related to the
Expand All @@ -278,7 +278,7 @@ void AArch64ConditionOptimizer::modifyCmp(MachineInstr *CmpMI,
// Change condition in branch instruction.
BuildMI(*MBB, BrMI, BrMI.getDebugLoc(), TII->get(AArch64::Bcc))
.addImm(Cmp)
.addOperand(BrMI.getOperand(1));
.add(BrMI.getOperand(1));
BrMI.eraseFromParent();

MBB->updateTerminator();
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11 changes: 5 additions & 6 deletions llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
View file
Expand Up @@ -594,7 +594,7 @@ void SSACCmpConv::convert(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks) {
// Insert a SUBS Rn, #0 instruction instead of the cbz / cbnz.
BuildMI(*Head, Head->end(), TermDL, MCID)
.addReg(DestReg, RegState::Define | RegState::Dead)
.addOperand(HeadCond[2])
.add(HeadCond[2])
.addImm(0)
.addImm(0);
// SUBS uses the GPR*sp register classes.
Expand Down Expand Up @@ -650,13 +650,12 @@ void SSACCmpConv::convert(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks) {
if (CmpMI->getOperand(FirstOp + 1).isReg())
MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),
TII->getRegClass(MCID, 1, TRI, *MF));
MachineInstrBuilder MIB =
BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)
.addOperand(CmpMI->getOperand(FirstOp)); // Register Rn
MachineInstrBuilder MIB = BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)
.add(CmpMI->getOperand(FirstOp)); // Register Rn
if (isZBranch)
MIB.addImm(0); // cbz/cbnz Rn -> ccmp Rn, #0
else
MIB.addOperand(CmpMI->getOperand(FirstOp + 1)); // Register Rm / Immediate
MIB.add(CmpMI->getOperand(FirstOp + 1)); // Register Rm / Immediate
MIB.addImm(NZCV).addImm(HeadCmpBBCC);

// If CmpMI was a terminator, we need a new conditional branch to replace it.
Expand All @@ -666,7 +665,7 @@ void SSACCmpConv::convert(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks) {
CmpMI->getOpcode() == AArch64::CBNZX;
BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), TII->get(AArch64::Bcc))
.addImm(isNZ ? AArch64CC::NE : AArch64CC::EQ)
.addOperand(CmpMI->getOperand(1)); // Branch target.
.add(CmpMI->getOperand(1)); // Branch target.
}
CmpMI->eraseFromParent();
Head->updateTerminator();
Expand Down
40 changes: 19 additions & 21 deletions llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
View file
Expand Up @@ -70,9 +70,9 @@ static void transferImpOps(MachineInstr &OldMI, MachineInstrBuilder &UseMI,
const MachineOperand &MO = OldMI.getOperand(i);
assert(MO.isReg() && MO.getReg());
if (MO.isUse())
UseMI.addOperand(MO);
UseMI.add(MO);
else
DefMI.addOperand(MO);
DefMI.add(MO);
}
}

Expand Down Expand Up @@ -112,7 +112,7 @@ static bool tryOrrMovk(uint64_t UImm, uint64_t OrrImm, MachineInstr &MI,
// Create the ORR-immediate instruction.
MachineInstrBuilder MIB =
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
.addOperand(MI.getOperand(0))
.add(MI.getOperand(0))
.addReg(AArch64::XZR)
.addImm(Encoding);

Expand Down Expand Up @@ -179,7 +179,7 @@ static bool tryToreplicateChunks(uint64_t UImm, MachineInstr &MI,
// Create the ORR-immediate instruction.
MachineInstrBuilder MIB =
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
.addOperand(MI.getOperand(0))
.add(MI.getOperand(0))
.addReg(AArch64::XZR)
.addImm(Encoding);

Expand Down Expand Up @@ -362,7 +362,7 @@ static bool trySequenceOfOnes(uint64_t UImm, MachineInstr &MI,
AArch64_AM::processLogicalImmediate(OrrImm, 64, Encoding);
MachineInstrBuilder MIB =
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
.addOperand(MI.getOperand(0))
.add(MI.getOperand(0))
.addReg(AArch64::XZR)
.addImm(Encoding);

Expand Down Expand Up @@ -425,7 +425,7 @@ bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
unsigned Opc = (BitSize == 32 ? AArch64::ORRWri : AArch64::ORRXri);
MachineInstrBuilder MIB =
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
.addOperand(MI.getOperand(0))
.add(MI.getOperand(0))
.addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
.addImm(Encoding);
transferImpOps(MI, MIB, MIB);
Expand Down Expand Up @@ -627,7 +627,7 @@ bool AArch64ExpandPseudo::expandCMP_SWAP(
.addReg(Addr.getReg());
BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg)
.addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
.addOperand(Desired)
.add(Desired)
.addImm(ExtendImm);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc))
.addImm(AArch64CC::NE)
Expand All @@ -643,9 +643,7 @@ bool AArch64ExpandPseudo::expandCMP_SWAP(
StoreBB->addLiveIn(New.getReg());
addPostLoopLiveIns(StoreBB, LiveRegs);

BuildMI(StoreBB, DL, TII->get(StlrOp), StatusReg)
.addOperand(New)
.addOperand(Addr);
BuildMI(StoreBB, DL, TII->get(StlrOp), StatusReg).add(New).add(Addr);
BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
.addReg(StatusReg, RegState::Kill)
.addMBB(LoadCmpBB);
Expand Down Expand Up @@ -710,15 +708,15 @@ bool AArch64ExpandPseudo::expandCMP_SWAP_128(
.addReg(Addr.getReg());
BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
.addReg(DestLo.getReg(), getKillRegState(DestLo.isDead()))
.addOperand(DesiredLo)
.add(DesiredLo)
.addImm(0);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
.addUse(AArch64::WZR)
.addUse(AArch64::WZR)
.addImm(AArch64CC::EQ);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
.addReg(DestHi.getReg(), getKillRegState(DestHi.isDead()))
.addOperand(DesiredHi)
.add(DesiredHi)
.addImm(0);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
.addUse(StatusReg, RegState::Kill)
Expand All @@ -738,9 +736,9 @@ bool AArch64ExpandPseudo::expandCMP_SWAP_128(
StoreBB->addLiveIn(NewHi.getReg());
addPostLoopLiveIns(StoreBB, LiveRegs);
BuildMI(StoreBB, DL, TII->get(AArch64::STLXPX), StatusReg)
.addOperand(NewLo)
.addOperand(NewHi)
.addOperand(Addr);
.add(NewLo)
.add(NewHi)
.add(Addr);
BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
.addReg(StatusReg, RegState::Kill)
.addMBB(LoadCmpBB);
Expand Down Expand Up @@ -825,8 +823,8 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
MachineInstrBuilder MIB1 =
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode),
MI.getOperand(0).getReg())
.addOperand(MI.getOperand(1))
.addOperand(MI.getOperand(2))
.add(MI.getOperand(1))
.add(MI.getOperand(2))
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
transferImpOps(MI, MIB1, MIB1);
MI.eraseFromParent();
Expand All @@ -842,7 +840,7 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg);
MachineInstrBuilder MIB2 =
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::LDRXui))
.addOperand(MI.getOperand(0))
.add(MI.getOperand(0))
.addReg(DstReg);

if (MO1.isGlobal()) {
Expand Down Expand Up @@ -878,13 +876,13 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
unsigned DstReg = MI.getOperand(0).getReg();
MachineInstrBuilder MIB1 =
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg)
.addOperand(MI.getOperand(1));
.add(MI.getOperand(1));

MachineInstrBuilder MIB2 =
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
.addOperand(MI.getOperand(0))
.add(MI.getOperand(0))
.addReg(DstReg)
.addOperand(MI.getOperand(2))
.add(MI.getOperand(2))
.addImm(0);

transferImpOps(MI, MIB1, MIB2);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
View file
Expand Up @@ -362,7 +362,7 @@ static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec(
unsigned OpndIdx = 0;
for (unsigned OpndEnd = MBBI->getNumOperands() - 1; OpndIdx < OpndEnd;
++OpndIdx)
MIB.addOperand(MBBI->getOperand(OpndIdx));
MIB.add(MBBI->getOperand(OpndIdx));

assert(MBBI->getOperand(OpndIdx).getImm() == 0 &&
"Unexpected immediate offset in first/last callee-save save/restore "
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
View file
Expand Up @@ -369,7 +369,7 @@ void AArch64InstrInfo::instantiateCondBranch(
// Folded compare-and-branch
// Note that we use addOperand instead of addReg to keep the flags.
const MachineInstrBuilder MIB =
BuildMI(&MBB, DL, get(Cond[1].getImm())).addOperand(Cond[2]);
BuildMI(&MBB, DL, get(Cond[1].getImm())).add(Cond[2]);
if (Cond.size() > 3)
MIB.addImm(Cond[3].getImm());
MIB.addMBB(TBB);
Expand Down Expand Up @@ -3793,7 +3793,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
MachineInstrBuilder MIB1 =
BuildMI(MF, Root.getDebugLoc(), TII->get(SubOpc), NewVR)
.addReg(ZeroReg)
.addOperand(Root.getOperand(2));
.add(Root.getOperand(2));
InsInstrs.push_back(MIB1);
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC);
Expand Down

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