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Second Recommit "[AArch64] Split bitmask immediate of bitwise AND ope…
…ration" This reverts the revert commit c07f709 with bug fixes. Differential Revision: https://reviews.llvm.org/D109963
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//===- AArch64MIPeepholeOpt.cpp - AArch64 MI peephole optimization pass ---===// | ||
// | ||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
// See https://llvm.org/LICENSE.txt for license information. | ||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
// | ||
//===----------------------------------------------------------------------===// | ||
// | ||
// This pass performs below peephole optimizations on MIR level. | ||
// | ||
// 1. MOVi32imm + ANDWrr ==> ANDWri + ANDWri | ||
// MOVi64imm + ANDXrr ==> ANDXri + ANDXri | ||
// | ||
// The mov pseudo instruction could be expanded to multiple mov instructions | ||
// later. In this case, we could try to split the constant operand of mov | ||
// instruction into two bitmask immediates. It makes two AND instructions | ||
// intead of multiple `mov` + `and` instructions. | ||
//===----------------------------------------------------------------------===// | ||
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#include "AArch64ExpandImm.h" | ||
#include "AArch64InstrInfo.h" | ||
#include "MCTargetDesc/AArch64AddressingModes.h" | ||
#include "llvm/ADT/SetVector.h" | ||
#include "llvm/CodeGen/MachineDominators.h" | ||
#include "llvm/CodeGen/MachineLoopInfo.h" | ||
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using namespace llvm; | ||
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#define DEBUG_TYPE "aarch64-mi-peephole-opt" | ||
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namespace { | ||
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struct AArch64MIPeepholeOpt : public MachineFunctionPass { | ||
static char ID; | ||
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AArch64MIPeepholeOpt() : MachineFunctionPass(ID) { | ||
initializeAArch64MIPeepholeOptPass(*PassRegistry::getPassRegistry()); | ||
} | ||
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const AArch64InstrInfo *TII; | ||
MachineLoopInfo *MLI; | ||
MachineRegisterInfo *MRI; | ||
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template <typename T> | ||
bool visitAND(MachineInstr &MI, | ||
SmallSetVector<MachineInstr *, 8> &ToBeRemoved); | ||
bool runOnMachineFunction(MachineFunction &MF) override; | ||
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StringRef getPassName() const override { | ||
return "AArch64 MI Peephole Optimization pass"; | ||
} | ||
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void getAnalysisUsage(AnalysisUsage &AU) const override { | ||
AU.setPreservesCFG(); | ||
AU.addRequired<MachineLoopInfo>(); | ||
MachineFunctionPass::getAnalysisUsage(AU); | ||
} | ||
}; | ||
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char AArch64MIPeepholeOpt::ID = 0; | ||
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} // end anonymous namespace | ||
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INITIALIZE_PASS(AArch64MIPeepholeOpt, "aarch64-mi-peephole-opt", | ||
"AArch64 MI Peephole Optimization", false, false) | ||
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template <typename T> | ||
static bool splitBitmaskImm(T Imm, unsigned RegSize, T &Imm1Enc, T &Imm2Enc) { | ||
T UImm = static_cast<T>(Imm); | ||
if (AArch64_AM::isLogicalImmediate(UImm, RegSize)) | ||
return false; | ||
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// If this immediate can be handled by one instruction, do not split it. | ||
SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn; | ||
AArch64_IMM::expandMOVImm(UImm, RegSize, Insn); | ||
if (Insn.size() == 1) | ||
return false; | ||
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// The bitmask immediate consists of consecutive ones. Let's say there is | ||
// constant 0b00000000001000000000010000000000 which does not consist of | ||
// consecutive ones. We can split it in to two bitmask immediate like | ||
// 0b00000000001111111111110000000000 and 0b11111111111000000000011111111111. | ||
// If we do AND with these two bitmask immediate, we can see original one. | ||
unsigned LowestBitSet = countTrailingZeros(UImm); | ||
unsigned HighestBitSet = Log2_64(UImm); | ||
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// Create a mask which is filled with one from the position of lowest bit set | ||
// to the position of highest bit set. | ||
T NewImm1 = (static_cast<T>(2) << HighestBitSet) - | ||
(static_cast<T>(1) << LowestBitSet); | ||
// Create a mask which is filled with one outside the position of lowest bit | ||
// set and the position of highest bit set. | ||
T NewImm2 = UImm | ~NewImm1; | ||
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// If the split value is not valid bitmask immediate, do not split this | ||
// constant. | ||
if (!AArch64_AM::isLogicalImmediate(NewImm2, RegSize)) | ||
return false; | ||
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Imm1Enc = AArch64_AM::encodeLogicalImmediate(NewImm1, RegSize); | ||
Imm2Enc = AArch64_AM::encodeLogicalImmediate(NewImm2, RegSize); | ||
return true; | ||
} | ||
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template <typename T> | ||
bool AArch64MIPeepholeOpt::visitAND( | ||
MachineInstr &MI, SmallSetVector<MachineInstr *, 8> &ToBeRemoved) { | ||
// Try below transformation. | ||
// | ||
// MOVi32imm + ANDWrr ==> ANDWri + ANDWri | ||
// MOVi64imm + ANDXrr ==> ANDXri + ANDXri | ||
// | ||
// The mov pseudo instruction could be expanded to multiple mov instructions | ||
// later. Let's try to split the constant operand of mov instruction into two | ||
// bitmask immediates. It makes only two AND instructions intead of multiple | ||
// mov + and instructions. | ||
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unsigned RegSize = sizeof(T) * 8; | ||
assert((RegSize == 32 || RegSize == 64) && | ||
"Invalid RegSize for AND bitmask peephole optimization"); | ||
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// Check whether AND's MBB is in loop and the AND is loop invariant. | ||
MachineBasicBlock *MBB = MI.getParent(); | ||
MachineLoop *L = MLI->getLoopFor(MBB); | ||
if (L && !L->isLoopInvariant(MI)) | ||
return false; | ||
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// Check whether AND's operand is MOV with immediate. | ||
MachineInstr *MovMI = MRI->getUniqueVRegDef(MI.getOperand(2).getReg()); | ||
MachineInstr *SubregToRegMI = nullptr; | ||
// If it is SUBREG_TO_REG, check its operand. | ||
if (MovMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) { | ||
SubregToRegMI = MovMI; | ||
MovMI = MRI->getUniqueVRegDef(MovMI->getOperand(2).getReg()); | ||
} | ||
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if (MovMI->getOpcode() != AArch64::MOVi32imm && | ||
MovMI->getOpcode() != AArch64::MOVi64imm) | ||
return false; | ||
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// If the MOV has multiple uses, do not split the immediate because it causes | ||
// more instructions. | ||
if (!MRI->hasOneUse(MovMI->getOperand(0).getReg())) | ||
return false; | ||
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if (SubregToRegMI && !MRI->hasOneUse(SubregToRegMI->getOperand(0).getReg())) | ||
return false; | ||
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// Split the bitmask immediate into two. | ||
T UImm = static_cast<T>(MovMI->getOperand(1).getImm()); | ||
T Imm1Enc; | ||
T Imm2Enc; | ||
if (!splitBitmaskImm(UImm, RegSize, Imm1Enc, Imm2Enc)) | ||
return false; | ||
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// Create new AND MIs. | ||
DebugLoc DL = MI.getDebugLoc(); | ||
const TargetRegisterClass *ANDImmRC = | ||
(RegSize == 32) ? &AArch64::GPR32spRegClass : &AArch64::GPR64spRegClass; | ||
Register DstReg = MI.getOperand(0).getReg(); | ||
Register SrcReg = MI.getOperand(1).getReg(); | ||
Register NewTmpReg = MRI->createVirtualRegister(ANDImmRC); | ||
unsigned Opcode = (RegSize == 32) ? AArch64::ANDWri : AArch64::ANDXri; | ||
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MRI->constrainRegClass(NewTmpReg, MRI->getRegClass(SrcReg)); | ||
BuildMI(*MBB, MI, DL, TII->get(Opcode), NewTmpReg) | ||
.addReg(SrcReg) | ||
.addImm(Imm1Enc); | ||
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MRI->constrainRegClass(DstReg, ANDImmRC); | ||
BuildMI(*MBB, MI, DL, TII->get(Opcode), DstReg) | ||
.addReg(NewTmpReg) | ||
.addImm(Imm2Enc); | ||
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ToBeRemoved.insert(&MI); | ||
if (SubregToRegMI) | ||
ToBeRemoved.insert(SubregToRegMI); | ||
ToBeRemoved.insert(MovMI); | ||
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return true; | ||
} | ||
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bool AArch64MIPeepholeOpt::runOnMachineFunction(MachineFunction &MF) { | ||
if (skipFunction(MF.getFunction())) | ||
return false; | ||
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TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); | ||
MLI = &getAnalysis<MachineLoopInfo>(); | ||
MRI = &MF.getRegInfo(); | ||
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if (!MRI->isSSA()) | ||
return false; | ||
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bool Changed = false; | ||
SmallSetVector<MachineInstr *, 8> ToBeRemoved; | ||
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for (MachineBasicBlock &MBB : MF) { | ||
for (MachineInstr &MI : MBB) { | ||
switch (MI.getOpcode()) { | ||
default: | ||
break; | ||
case AArch64::ANDWrr: | ||
Changed = visitAND<uint32_t>(MI, ToBeRemoved); | ||
break; | ||
case AArch64::ANDXrr: | ||
Changed = visitAND<uint64_t>(MI, ToBeRemoved); | ||
break; | ||
} | ||
} | ||
} | ||
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for (MachineInstr *MI : ToBeRemoved) | ||
MI->eraseFromParent(); | ||
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return Changed; | ||
} | ||
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FunctionPass *llvm::createAArch64MIPeepholeOptPass() { | ||
return new AArch64MIPeepholeOpt(); | ||
} |
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