[ARM] Remove condition that could never be true

From Arm v8 Architecture Reference Manual F5.1.84 LDREXD
The ldrexd instruction in Arm state has the following conditions:

t = UInt(Rt); t2 = t + 1; n = UInt(Rn);
if Rt<0> == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;

In when Rt is odd or if Rt is 14 (making t2 15).

In the implementation when the pair is the UNPREDICTABLE R14_R15 we
would ideally return SOFT_FAIL. We can't because there is no R14_R15
value for us to return so we fail early returning FAIL.

The early return for registers outside the bounds of the table means
the check for Rt == 14 (0xE) redundant which causes a static analyzer
to flag the condition as never being true.

To fix the warning I've removed the check and replaced with a comment
explaining the difference with the specification.

Fixes pr41660

Differential Revision: https://reviews.llvm.org/D77463

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

@@ -1225,10 +1225,12 @@ static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
+  // According to the Arm ARM RegNo = 14 is undefined, but we return fail
+  // rather than SoftFail as there is no GPRPair table entry for index 7.
   if (RegNo > 13)
     return MCDisassembler::Fail;
 
-  if ((RegNo & 1) || RegNo == 0xe)
+  if (RegNo & 1)
      S = MCDisassembler::SoftFail;
 
   unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];

llvm/test/MC/Disassembler/ARM/invalid-armv7.txt

@@ -146,7 +146,30 @@
 # CHECK: potentially undefined instruction encoding
 # CHECK-NEXT: [0x05 0x70 0xd7 0xe6]
 
+#------------------------------------------------------------------------------
+# Undefined encodings for ldrexd
+#------------------------------------------------------------------------------
 
+# Opcode=242 Name=LDREXD Format=ARM_FORMAT_LDSTEX(6)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+
+# ARM v8 Architecture Reference Manual F5.1.84 LDREXD
+# t = UInt(Rt); t2 = t + 1; n = UInt(Rn);
+# if Rt<0> == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;
+
+[0x9f 0x1f 0xb3 0xe1]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x9f 0x1f 0xb3 0xe1]
+
+# FIXME: should be potentially undefined but no register pair R14_R15 defined to
+# to return.
+[0x9f 0xef 0xb3 0xe1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x9f 0xef 0xb3 0xe1]
 
 #------------------------------------------------------------------------------
 # Undefined encodings for mcr