Skip to content

Commit

Permalink
clang: Update tests after InstSimplify change
Browse files Browse the repository at this point in the history 
Update tests after 1536e29
  • Loading branch information
@arsenm
arsenm committed Jun 2, 2023
1 parent 456468a commit 14c44df
Show file tree
Hide file tree
Showing 2 changed files with 178 additions and 179 deletions.
98 changes: 49 additions & 49 deletions clang/test/CodeGen/arm_acle.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -145,7 +145,7 @@ void test_dbg(void) {
// AArch32-NEXT: [[LDREX_I:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) [[P:%.*]])
// AArch32-NEXT: [[STREX_I:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[X:%.*]], ptr elementtype(i32) [[P]])
// AArch32-NEXT: [[TOBOOL_I:%.*]] = icmp ne i32 [[STREX_I]], 0
// AArch32-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], !llvm.loop [[LOOP7:![0-9]+]]
// AArch32-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], !llvm.loop [[LOOP3:![0-9]+]]
// AArch32: __swp.exit:
// AArch32-NEXT: ret void
//
Expand All @@ -154,11 +154,11 @@ void test_dbg(void) {
// AArch64-NEXT: br label [[DO_BODY_I:%.*]]
// AArch64: do.body.i:
// AArch64-NEXT: [[LDXR_I:%.*]] = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i32) [[P:%.*]])
// AArch64-NEXT: [[TMP1:%.*]] = trunc i64 [[LDXR_I]] to i32
// AArch64-NEXT: [[TMP2:%.*]] = zext i32 [[X:%.*]] to i64
// AArch64-NEXT: [[STXR_I:%.*]] = call i32 @llvm.aarch64.stxr.p0(i64 [[TMP2]], ptr elementtype(i32) [[P]])
// AArch64-NEXT: [[TMP0:%.*]] = trunc i64 [[LDXR_I]] to i32
// AArch64-NEXT: [[TMP1:%.*]] = zext i32 [[X:%.*]] to i64
// AArch64-NEXT: [[STXR_I:%.*]] = call i32 @llvm.aarch64.stxr.p0(i64 [[TMP1]], ptr elementtype(i32) [[P]])
// AArch64-NEXT: [[TOBOOL_I:%.*]] = icmp ne i32 [[STXR_I]], 0
// AArch64-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], !llvm.loop [[LOOP6:![0-9]+]]
// AArch64-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], !llvm.loop [[LOOP2:![0-9]+]]
// AArch64: __swp.exit:
// AArch64-NEXT: ret void
//
Expand Down Expand Up @@ -484,17 +484,17 @@ uint32_t test_rev16(uint32_t t) {
// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV_I]])
// AArch64-NEXT: [[REM_I_I10_I:%.*]] = urem i32 16, 32
// AArch64-NEXT: [[CMP_I_I11_I:%.*]] = icmp eq i32 [[REM_I_I10_I]], 0
// AArch64-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I12_I:%.*]], label [[IF_END_I_I17_I:%.*]]
// AArch64: if.then.i.i12.i:
// AArch64-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I17_I:%.*]], label [[IF_END_I_I12_I:%.*]]
// AArch64: if.then.i.i17.i:
// AArch64-NEXT: br label [[__REV16_EXIT18_I:%.*]]
// AArch64: if.end.i.i17.i:
// AArch64: if.end.i.i12.i:
// AArch64-NEXT: [[SHR_I_I13_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I10_I]]
// AArch64-NEXT: [[SUB_I_I14_I:%.*]] = sub i32 32, [[REM_I_I10_I]]
// AArch64-NEXT: [[SHL_I_I15_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I14_I]]
// AArch64-NEXT: [[OR_I_I16_I:%.*]] = or i32 [[SHR_I_I13_I]], [[SHL_I_I15_I]]
// AArch64-NEXT: br label [[__REV16_EXIT18_I]]
// AArch64: __rev16.exit18.i:
// AArch64-NEXT: [[RETVAL_I_I6_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I12_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I17_I]] ]
// AArch64-NEXT: [[RETVAL_I_I6_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I17_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I12_I]] ]
// AArch64-NEXT: [[CONV1_I:%.*]] = zext i32 [[RETVAL_I_I6_I_0]] to i64
// AArch64-NEXT: [[SHL_I:%.*]] = shl i64 [[CONV1_I]], 32
// AArch64-NEXT: [[CONV2_I:%.*]] = trunc i64 [[T]] to i32
Expand Down Expand Up @@ -527,17 +527,17 @@ long test_rev16l(long t) {
// ARM-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV_I]])
// ARM-NEXT: [[REM_I_I10_I:%.*]] = urem i32 16, 32
// ARM-NEXT: [[CMP_I_I11_I:%.*]] = icmp eq i32 [[REM_I_I10_I]], 0
// ARM-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I12_I:%.*]], label [[IF_END_I_I17_I:%.*]]
// ARM: if.then.i.i12.i:
// ARM-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I17_I:%.*]], label [[IF_END_I_I12_I:%.*]]
// ARM: if.then.i.i17.i:
// ARM-NEXT: br label [[__REV16_EXIT18_I:%.*]]
// ARM: if.end.i.i17.i:
// ARM: if.end.i.i12.i:
// ARM-NEXT: [[SHR_I_I13_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I10_I]]
// ARM-NEXT: [[SUB_I_I14_I:%.*]] = sub i32 32, [[REM_I_I10_I]]
// ARM-NEXT: [[SHL_I_I15_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I14_I]]
// ARM-NEXT: [[OR_I_I16_I:%.*]] = or i32 [[SHR_I_I13_I]], [[SHL_I_I15_I]]
// ARM-NEXT: br label [[__REV16_EXIT18_I]]
// ARM: __rev16.exit18.i:
// ARM-NEXT: [[RETVAL_I_I6_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I12_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I17_I]] ]
// ARM-NEXT: [[RETVAL_I_I6_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I17_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I12_I]] ]
// ARM-NEXT: [[CONV1_I:%.*]] = zext i32 [[RETVAL_I_I6_I_0]] to i64
// ARM-NEXT: [[SHL_I:%.*]] = shl i64 [[CONV1_I]], 32
// ARM-NEXT: [[CONV2_I:%.*]] = trunc i64 [[T]] to i32
Expand Down Expand Up @@ -662,7 +662,7 @@ int32_t test_qsub(int32_t a, int32_t b) {
extern int32_t f();
// AArch32-LABEL: @test_qdbl(
// AArch32-NEXT: entry:
// AArch32-NEXT: [[CALL:%.*]] = call i32 @f() #[[ATTR7:[0-9]+]]
// AArch32-NEXT: [[CALL:%.*]] = call i32 @f() #[[ATTR9:[0-9]+]]
// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qadd(i32 [[CALL]], i32 [[CALL]])
// AArch32-NEXT: ret i32 [[TMP0]]
//
Expand Down Expand Up @@ -1456,12 +1456,12 @@ uint32_t test_crc32cd(uint32_t a, uint64_t b) {
/* 10.1 Special register intrinsics */
// AArch32-LABEL: @test_rsr(
// AArch32-NEXT: entry:
// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META9:![0-9]+]])
// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META5:![0-9]+]])
// AArch32-NEXT: ret i32 [[TMP0]]
//
// AArch64-LABEL: @test_rsr(
// AArch64-NEXT: entry:
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META8:![0-9]+]])
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4:![0-9]+]])
// AArch64-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
// AArch64-NEXT: ret i32 [[TMP1]]
//
Expand All @@ -1475,12 +1475,12 @@ uint32_t test_rsr() {

// AArch32-LABEL: @test_rsr64(
// AArch32-NEXT: entry:
// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META10:![0-9]+]])
// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META6:![0-9]+]])
// AArch32-NEXT: ret i64 [[TMP0]]
//
// AArch64-LABEL: @test_rsr64(
// AArch64-NEXT: entry:
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META8]])
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4]])
// AArch64-NEXT: ret i64 [[TMP0]]
//
uint64_t test_rsr64() {
Expand All @@ -1494,7 +1494,7 @@ uint64_t test_rsr64() {
#ifdef __ARM_FEATURE_SYSREG128
// AArch6494D128-LABEL: @test_rsr128(
// AArch6494D128-NEXT: entry:
// AArch6494D128-NEXT: [[TMP0:%.*]] = call i128 @llvm.read_volatile_register.i128(metadata [[META8]])
// AArch6494D128-NEXT: [[TMP0:%.*]] = call i128 @llvm.read_volatile_register.i128(metadata [[META4]])
// AArch6494D128-NEXT: ret i128 [[TMP0]]
//
__uint128_t test_rsr128() {
Expand All @@ -1504,13 +1504,13 @@ __uint128_t test_rsr128() {

// AArch32-LABEL: @test_rsrp(
// AArch32-NEXT: entry:
// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META11:![0-9]+]])
// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META7:![0-9]+]])
// AArch32-NEXT: [[TMP1:%.*]] = inttoptr i32 [[TMP0]] to ptr
// AArch32-NEXT: ret ptr [[TMP1]]
//
// AArch64-LABEL: @test_rsrp(
// AArch64-NEXT: entry:
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META9:![0-9]+]])
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META5:![0-9]+]])
// AArch64-NEXT: [[TMP1:%.*]] = inttoptr i64 [[TMP0]] to ptr
// AArch64-NEXT: ret ptr [[TMP1]]
//
Expand All @@ -1520,13 +1520,13 @@ void *test_rsrp() {

// AArch32-LABEL: @test_wsr(
// AArch32-NEXT: entry:
// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META9]], i32 [[V:%.*]])
// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META5]], i32 [[V:%.*]])
// AArch32-NEXT: ret void
//
// AArch64-LABEL: @test_wsr(
// AArch64-NEXT: entry:
// AArch64-NEXT: [[TMP0:%.*]] = zext i32 [[V:%.*]] to i64
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META8]], i64 [[TMP0]])
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[TMP0]])
// AArch64-NEXT: ret void
//
void test_wsr(uint32_t v) {
Expand All @@ -1539,12 +1539,12 @@ void test_wsr(uint32_t v) {

// AArch32-LABEL: @test_wsr64(
// AArch32-NEXT: entry:
// AArch32-NEXT: call void @llvm.write_register.i64(metadata [[META10]], i64 [[V:%.*]])
// AArch32-NEXT: call void @llvm.write_register.i64(metadata [[META6]], i64 [[V:%.*]])
// AArch32-NEXT: ret void
//
// AArch64-LABEL: @test_wsr64(
// AArch64-NEXT: entry:
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META8]], i64 [[V:%.*]])
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[V:%.*]])
// AArch64-NEXT: ret void
//
void test_wsr64(uint64_t v) {
Expand All @@ -1558,7 +1558,7 @@ void test_wsr64(uint64_t v) {
#ifdef __ARM_FEATURE_SYSREG128
// AArch6494D128-LABEL: @test_wsr128(
// AArch6494D128-NEXT: entry:
// AArch6494D128-NEXT: call void @llvm.write_register.i128(metadata [[META8]], i128 [[V:%.*]])
// AArch6494D128-NEXT: call void @llvm.write_register.i128(metadata [[META4]], i128 [[V:%.*]])
// AArch6494D128-NEXT: ret void
//
void test_wsr128(__uint128_t v) {
Expand All @@ -1570,13 +1570,13 @@ void test_wsr128(__uint128_t v) {
// AArch32-LABEL: @test_wsrp(
// AArch32-NEXT: entry:
// AArch32-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[V:%.*]] to i32
// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META11]], i32 [[TMP0]])
// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META7]], i32 [[TMP0]])
// AArch32-NEXT: ret void
//
// AArch64-LABEL: @test_wsrp(
// AArch64-NEXT: entry:
// AArch64-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[V:%.*]] to i64
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META9]], i64 [[TMP0]])
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META5]], i64 [[TMP0]])
// AArch64-NEXT: ret void
//
void test_wsrp(void *v) {
Expand All @@ -1586,19 +1586,19 @@ void test_wsrp(void *v) {
// AArch32-LABEL: @test_rsrf(
// AArch32-NEXT: entry:
// AArch32-NEXT: [[REF_TMP:%.*]] = alloca i32, align 4
// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META9]])
// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META5]])
// AArch32-NEXT: store i32 [[TMP0]], ptr [[REF_TMP]], align 4
// AArch32-NEXT: [[TMP2:%.*]] = load float, ptr [[REF_TMP]], align 4
// AArch32-NEXT: ret float [[TMP2]]
// AArch32-NEXT: [[TMP1:%.*]] = load float, ptr [[REF_TMP]], align 4
// AArch32-NEXT: ret float [[TMP1]]
//
// AArch64-LABEL: @test_rsrf(
// AArch64-NEXT: entry:
// AArch64-NEXT: [[REF_TMP:%.*]] = alloca i32, align 4
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META8]])
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4]])
// AArch64-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
// AArch64-NEXT: store i32 [[TMP1]], ptr [[REF_TMP]], align 4
// AArch64-NEXT: [[TMP3:%.*]] = load float, ptr [[REF_TMP]], align 4
// AArch64-NEXT: ret float [[TMP3]]
// AArch64-NEXT: [[TMP2:%.*]] = load float, ptr [[REF_TMP]], align 4
// AArch64-NEXT: ret float [[TMP2]]
//
float test_rsrf() {
#ifdef __ARM_32BIT_STATE
Expand All @@ -1611,18 +1611,18 @@ float test_rsrf() {
// AArch32-LABEL: @test_rsrf64(
// AArch32-NEXT: entry:
// AArch32-NEXT: [[REF_TMP:%.*]] = alloca i64, align 8
// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META10]])
// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META6]])
// AArch32-NEXT: store i64 [[TMP0]], ptr [[REF_TMP]], align 8
// AArch32-NEXT: [[TMP2:%.*]] = load double, ptr [[REF_TMP]], align 8
// AArch32-NEXT: ret double [[TMP2]]
// AArch32-NEXT: [[TMP1:%.*]] = load double, ptr [[REF_TMP]], align 8
// AArch32-NEXT: ret double [[TMP1]]
//
// AArch64-LABEL: @test_rsrf64(
// AArch64-NEXT: entry:
// AArch64-NEXT: [[REF_TMP:%.*]] = alloca i64, align 8
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META8]])
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4]])
// AArch64-NEXT: store i64 [[TMP0]], ptr [[REF_TMP]], align 8
// AArch64-NEXT: [[TMP2:%.*]] = load double, ptr [[REF_TMP]], align 8
// AArch64-NEXT: ret double [[TMP2]]
// AArch64-NEXT: [[TMP1:%.*]] = load double, ptr [[REF_TMP]], align 8
// AArch64-NEXT: ret double [[TMP1]]
//
double test_rsrf64() {
#ifdef __ARM_32BIT_STATE
Expand All @@ -1636,17 +1636,17 @@ double test_rsrf64() {
// AArch32-NEXT: entry:
// AArch32-NEXT: [[V_ADDR:%.*]] = alloca float, align 4
// AArch32-NEXT: store float [[V:%.*]], ptr [[V_ADDR]], align 4
// AArch32-NEXT: [[TMP1:%.*]] = load i32, ptr [[V_ADDR]], align 4
// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META9]], i32 [[TMP1]])
// AArch32-NEXT: [[TMP0:%.*]] = load i32, ptr [[V_ADDR]], align 4
// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META5]], i32 [[TMP0]])
// AArch32-NEXT: ret void
//
// AArch64-LABEL: @test_wsrf(
// AArch64-NEXT: entry:
// AArch64-NEXT: [[V_ADDR:%.*]] = alloca float, align 4
// AArch64-NEXT: store float [[V:%.*]], ptr [[V_ADDR]], align 4
// AArch64-NEXT: [[TMP1:%.*]] = load i32, ptr [[V_ADDR]], align 4
// AArch64-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META8]], i64 [[TMP2]])
// AArch64-NEXT: [[TMP0:%.*]] = load i32, ptr [[V_ADDR]], align 4
// AArch64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[TMP1]])
// AArch64-NEXT: ret void
//
void test_wsrf(float v) {
Expand All @@ -1661,16 +1661,16 @@ void test_wsrf(float v) {
// AArch32-NEXT: entry:
// AArch32-NEXT: [[V_ADDR:%.*]] = alloca double, align 8
// AArch32-NEXT: store double [[V:%.*]], ptr [[V_ADDR]], align 8
// AArch32-NEXT: [[TMP1:%.*]] = load i64, ptr [[V_ADDR]], align 8
// AArch32-NEXT: call void @llvm.write_register.i64(metadata [[META10]], i64 [[TMP1]])
// AArch32-NEXT: [[TMP0:%.*]] = load i64, ptr [[V_ADDR]], align 8
// AArch32-NEXT: call void @llvm.write_register.i64(metadata [[META6]], i64 [[TMP0]])
// AArch32-NEXT: ret void
//
// AArch64-LABEL: @test_wsrf64(
// AArch64-NEXT: entry:
// AArch64-NEXT: [[V_ADDR:%.*]] = alloca double, align 8
// AArch64-NEXT: store double [[V:%.*]], ptr [[V_ADDR]], align 8
// AArch64-NEXT: [[TMP1:%.*]] = load i64, ptr [[V_ADDR]], align 8
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META8]], i64 [[TMP1]])
// AArch64-NEXT: [[TMP0:%.*]] = load i64, ptr [[V_ADDR]], align 8
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[TMP0]])
// AArch64-NEXT: ret void
//
void test_wsrf64(double v) {
Expand Down

0 comments on commit 14c44df

Please sign in to comment.