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[AMDGPU] Re-auto-generate test checks
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jayfoad committed May 7, 2020
1 parent e3ffe72 commit 17e13da
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Showing 2 changed files with 15 additions and 15 deletions.
17 changes: 9 additions & 8 deletions llvm/test/CodeGen/AMDGPU/infinite-loop.ll
Expand Up @@ -84,13 +84,14 @@ define amdgpu_kernel void @infinite_loops(i32 addrspace(1)* %out) {
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, 0x378
; SI-NEXT: s_and_b64 vcc, exec, -1
; SI-NEXT: BB2_2:
; SI: s_waitcnt lgkmcnt(0)
; SI-NEXT: BB2_2: ; %loop2
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_cbranch_vccnz BB2_2
; SI-NEXT: ; %bb.3:
; SI-NEXT: ; %bb.3: ; %Flow
; SI-NEXT: s_mov_b64 s[2:3], 0
; SI-NEXT: BB2_4:
; SI-NEXT: BB2_4: ; %Flow2
; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 vcc, vcc
Expand All @@ -101,12 +102,12 @@ define amdgpu_kernel void @infinite_loops(i32 addrspace(1)* %out) {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
; SI-NEXT: s_and_b64 vcc, exec, 0
; SI-NEXT: BB2_6:
; SI: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: BB2_6: ; %loop1
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_cbranch_vccz BB2_6
; SI-NEXT: BB2_7:
; SI-NEXT: BB2_7: ; %DummyReturnBlock
; SI-NEXT: s_endpgm

; IR-LABEL: @infinite_loops(
; IR-NEXT: entry:
; IR-NEXT: br i1 undef, label [[LOOP1:%.*]], label [[LOOP2:%.*]]
Expand Down
13 changes: 6 additions & 7 deletions llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
Expand Up @@ -145,31 +145,30 @@ define amdgpu_kernel void @nested_loop_conditions(i64 addrspace(1)* nocapture %a
; GCN-NEXT: v_cmp_lt_i32_e32 vcc, 8, v0
; GCN-NEXT: s_and_b64 vcc, exec, vcc
; GCN-NEXT: s_cbranch_vccnz BB1_6

; GCN-NEXT: ; %bb.1: ; %bb14.lr.ph
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0
; GCN-NEXT: s_branch BB1_3
; GCN-NEXT: BB1_2: ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT: BB1_2: ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT: s_mov_b64 s[0:1], -1
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: s_cbranch_execnz BB1_6
; GCN-NEXT: BB1_3: ; %bb14
; GCN-NEXT: ; =>This Loop Header: Depth=1
; GCN-NEXT: ; Child Loop BB1_4 Depth 2
; GCN-NEXT: ; Child Loop BB1_4 Depth 2
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 1, v0
; GCN-NEXT: s_and_b64 vcc, exec, vcc
; GCN-NEXT: s_cbranch_vccnz BB1_2
; GCN-NEXT: BB1_4: ; %bb18
; GCN-NEXT: ; Parent Loop BB1_3 Depth=1
; GCN-NEXT: ; => This Inner Loop Header: Depth=2
; GCN-NEXT: ; Parent Loop BB1_3 Depth=1
; GCN-NEXT: ; => This Inner Loop Header: Depth=2
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_lt_i32_e32 vcc, 8, v0
; GCN-NEXT: s_and_b64 vcc, exec, vcc
; GCN-NEXT: s_cbranch_vccnz BB1_4
; GCN-NEXT: ; %bb.5: ; %bb21
; GCN-NEXT: ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT: ; %bb.5: ; %bb21
; GCN-NEXT: ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0
; GCN-NEXT: s_waitcnt vmcnt(0)
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