Skip to content

Commit

Permalink
[RISCV] Removed the requirement of XLenVT for performSELECTCombine.
Browse files Browse the repository at this point in the history 
Reviewed By: Craig Topper

Differential Revision: https://reviews.llvm.org/D153044
  • Loading branch information
@mgudim
mgudim committed Jul 12, 2023
1 parent 2b2e7f6 commit 17e2df6
Show file tree
Hide file tree
Showing 4 changed files with 75 additions and 129 deletions.
4 changes: 0 additions & 4 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12135,10 +12135,6 @@ static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
if (Subtarget.hasShortForwardBranchOpt())
return SDValue();

// Only support XLenVT.
if (N->getValueType(0) != Subtarget.getXLenVT())
return SDValue();

SDValue TrueVal = N->getOperand(1);
SDValue FalseVal = N->getOperand(2);
if (SDValue V = tryFoldSelectIntoOp(N, DAG, TrueVal, FalseVal, /*Swapped*/false))
Expand Down
88 changes: 32 additions & 56 deletions llvm/test/CodeGen/RISCV/condops.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -69,17 +69,12 @@ define i64 @add1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
;
; RV32ZICOND-LABEL: add1:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: add a4, a2, a4
; RV32ZICOND-NEXT: add a3, a1, a3
; RV32ZICOND-NEXT: sltu a5, a3, a1
; RV32ZICOND-NEXT: add a4, a4, a5
; RV32ZICOND-NEXT: czero.nez a1, a1, a0
; RV32ZICOND-NEXT: czero.eqz a3, a3, a0
; RV32ZICOND-NEXT: or a3, a3, a1
; RV32ZICOND-NEXT: czero.eqz a1, a4, a0
; RV32ZICOND-NEXT: czero.nez a0, a2, a0
; RV32ZICOND-NEXT: or a1, a1, a0
; RV32ZICOND-NEXT: mv a0, a3
; RV32ZICOND-NEXT: czero.eqz a4, a4, a0
; RV32ZICOND-NEXT: add a2, a2, a4
; RV32ZICOND-NEXT: czero.eqz a0, a3, a0
; RV32ZICOND-NEXT: add a0, a1, a0
; RV32ZICOND-NEXT: sltu a1, a0, a1
; RV32ZICOND-NEXT: add a1, a2, a1
; RV32ZICOND-NEXT: ret
;
; RV64ZICOND-LABEL: add1:
Expand Down Expand Up @@ -107,17 +102,12 @@ define i64 @add2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
;
; RV32ZICOND-LABEL: add2:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: add a2, a2, a4
; RV32ZICOND-NEXT: add a5, a1, a3
; RV32ZICOND-NEXT: sltu a1, a5, a1
; RV32ZICOND-NEXT: czero.eqz a2, a2, a0
; RV32ZICOND-NEXT: add a2, a4, a2
; RV32ZICOND-NEXT: czero.eqz a0, a1, a0
; RV32ZICOND-NEXT: add a0, a3, a0
; RV32ZICOND-NEXT: sltu a1, a0, a3
; RV32ZICOND-NEXT: add a1, a2, a1
; RV32ZICOND-NEXT: czero.nez a2, a3, a0
; RV32ZICOND-NEXT: czero.eqz a3, a5, a0
; RV32ZICOND-NEXT: or a2, a3, a2
; RV32ZICOND-NEXT: czero.eqz a1, a1, a0
; RV32ZICOND-NEXT: czero.nez a0, a4, a0
; RV32ZICOND-NEXT: or a1, a1, a0
; RV32ZICOND-NEXT: mv a0, a2
; RV32ZICOND-NEXT: ret
;
; RV64ZICOND-LABEL: add2:
Expand Down Expand Up @@ -145,17 +135,12 @@ define i64 @add3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
;
; RV32ZICOND-LABEL: add3:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: add a4, a2, a4
; RV32ZICOND-NEXT: add a3, a1, a3
; RV32ZICOND-NEXT: sltu a5, a3, a1
; RV32ZICOND-NEXT: add a4, a4, a5
; RV32ZICOND-NEXT: czero.eqz a1, a1, a0
; RV32ZICOND-NEXT: czero.nez a3, a3, a0
; RV32ZICOND-NEXT: or a3, a1, a3
; RV32ZICOND-NEXT: czero.nez a1, a4, a0
; RV32ZICOND-NEXT: czero.eqz a0, a2, a0
; RV32ZICOND-NEXT: or a1, a0, a1
; RV32ZICOND-NEXT: mv a0, a3
; RV32ZICOND-NEXT: czero.nez a4, a4, a0
; RV32ZICOND-NEXT: add a2, a2, a4
; RV32ZICOND-NEXT: czero.nez a0, a3, a0
; RV32ZICOND-NEXT: add a0, a1, a0
; RV32ZICOND-NEXT: sltu a1, a0, a1
; RV32ZICOND-NEXT: add a1, a2, a1
; RV32ZICOND-NEXT: ret
;
; RV64ZICOND-LABEL: add3:
Expand Down Expand Up @@ -183,17 +168,12 @@ define i64 @add4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
;
; RV32ZICOND-LABEL: add4:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: add a2, a2, a4
; RV32ZICOND-NEXT: add a5, a1, a3
; RV32ZICOND-NEXT: sltu a1, a5, a1
; RV32ZICOND-NEXT: czero.nez a2, a2, a0
; RV32ZICOND-NEXT: add a2, a4, a2
; RV32ZICOND-NEXT: czero.nez a0, a1, a0
; RV32ZICOND-NEXT: add a0, a3, a0
; RV32ZICOND-NEXT: sltu a1, a0, a3
; RV32ZICOND-NEXT: add a1, a2, a1
; RV32ZICOND-NEXT: czero.eqz a2, a3, a0
; RV32ZICOND-NEXT: czero.nez a3, a5, a0
; RV32ZICOND-NEXT: or a2, a2, a3
; RV32ZICOND-NEXT: czero.nez a1, a1, a0
; RV32ZICOND-NEXT: czero.eqz a0, a4, a0
; RV32ZICOND-NEXT: or a1, a0, a1
; RV32ZICOND-NEXT: mv a0, a2
; RV32ZICOND-NEXT: ret
;
; RV64ZICOND-LABEL: add4:
Expand Down Expand Up @@ -221,14 +201,12 @@ define i64 @sub1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
;
; RV32ZICOND-LABEL: sub1:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: czero.eqz a3, a3, a0
; RV32ZICOND-NEXT: sltu a5, a1, a3
; RV32ZICOND-NEXT: sub a4, a2, a4
; RV32ZICOND-NEXT: sub a4, a4, a5
; RV32ZICOND-NEXT: czero.eqz a4, a4, a0
; RV32ZICOND-NEXT: czero.nez a2, a2, a0
; RV32ZICOND-NEXT: or a2, a4, a2
; RV32ZICOND-NEXT: czero.eqz a0, a3, a0
; RV32ZICOND-NEXT: sub a0, a1, a0
; RV32ZICOND-NEXT: czero.eqz a0, a4, a0
; RV32ZICOND-NEXT: sub a2, a2, a0
; RV32ZICOND-NEXT: sub a2, a2, a5
; RV32ZICOND-NEXT: sub a0, a1, a3
; RV32ZICOND-NEXT: mv a1, a2
; RV32ZICOND-NEXT: ret
;
Expand Down Expand Up @@ -257,14 +235,12 @@ define i64 @sub2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
;
; RV32ZICOND-LABEL: sub2:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: czero.nez a3, a3, a0
; RV32ZICOND-NEXT: sltu a5, a1, a3
; RV32ZICOND-NEXT: sub a4, a2, a4
; RV32ZICOND-NEXT: sub a4, a4, a5
; RV32ZICOND-NEXT: czero.nez a4, a4, a0
; RV32ZICOND-NEXT: czero.eqz a2, a2, a0
; RV32ZICOND-NEXT: or a2, a2, a4
; RV32ZICOND-NEXT: czero.nez a0, a3, a0
; RV32ZICOND-NEXT: sub a0, a1, a0
; RV32ZICOND-NEXT: czero.nez a0, a4, a0
; RV32ZICOND-NEXT: sub a2, a2, a0
; RV32ZICOND-NEXT: sub a2, a2, a5
; RV32ZICOND-NEXT: sub a0, a1, a3
; RV32ZICOND-NEXT: mv a1, a2
; RV32ZICOND-NEXT: ret
;
Expand Down
84 changes: 29 additions & 55 deletions llvm/test/CodeGen/RISCV/select.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -589,19 +589,15 @@ define i32 @select_add_1(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV64IM-LABEL: select_add_1:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: beqz a0, .LBB16_2
; RV64IM-NEXT: # %bb.1:
; RV64IM-NEXT: addw a2, a1, a2
; RV64IM-NEXT: .LBB16_2: # %entry
; RV64IM-NEXT: mv a0, a2
; RV64IM-NEXT: negw a0, a0
; RV64IM-NEXT: and a0, a0, a1
; RV64IM-NEXT: addw a0, a2, a0
; RV64IM-NEXT: ret
;
; RV64IMXVTCONDOPS-LABEL: select_add_1:
; RV64IMXVTCONDOPS: # %bb.0: # %entry
; RV64IMXVTCONDOPS-NEXT: addw a1, a1, a2
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0
; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0
; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2
; RV64IMXVTCONDOPS-NEXT: addw a0, a2, a0
; RV64IMXVTCONDOPS-NEXT: ret
;
; RV32IMZICOND-LABEL: select_add_1:
Expand All @@ -612,10 +608,8 @@ define i32 @select_add_1(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV64IMZICOND-LABEL: select_add_1:
; RV64IMZICOND: # %bb.0: # %entry
; RV64IMZICOND-NEXT: addw a1, a1, a2
; RV64IMZICOND-NEXT: czero.nez a2, a2, a0
; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0
; RV64IMZICOND-NEXT: or a0, a0, a2
; RV64IMZICOND-NEXT: addw a0, a2, a0
; RV64IMZICOND-NEXT: ret
entry:
%c = add i32 %a, %b
Expand All @@ -633,19 +627,15 @@ define i32 @select_add_2(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV64IM-LABEL: select_add_2:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: bnez a0, .LBB17_2
; RV64IM-NEXT: # %bb.1: # %entry
; RV64IM-NEXT: addw a1, a1, a2
; RV64IM-NEXT: .LBB17_2: # %entry
; RV64IM-NEXT: mv a0, a1
; RV64IM-NEXT: addiw a0, a0, -1
; RV64IM-NEXT: and a0, a0, a2
; RV64IM-NEXT: addw a0, a1, a0
; RV64IM-NEXT: ret
;
; RV64IMXVTCONDOPS-LABEL: select_add_2:
; RV64IMXVTCONDOPS: # %bb.0: # %entry
; RV64IMXVTCONDOPS-NEXT: addw a2, a1, a2
; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0
; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0
; RV64IMXVTCONDOPS-NEXT: addw a0, a1, a0
; RV64IMXVTCONDOPS-NEXT: ret
;
; RV32IMZICOND-LABEL: select_add_2:
Expand All @@ -656,10 +646,8 @@ define i32 @select_add_2(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV64IMZICOND-LABEL: select_add_2:
; RV64IMZICOND: # %bb.0: # %entry
; RV64IMZICOND-NEXT: addw a2, a1, a2
; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: or a0, a1, a0
; RV64IMZICOND-NEXT: addw a0, a1, a0
; RV64IMZICOND-NEXT: ret
entry:
%c = add i32 %a, %b
Expand All @@ -677,19 +665,16 @@ define i32 @select_add_3(i1 zeroext %cond, i32 %a) {
;
; RV64IM-LABEL: select_add_3:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: bnez a0, .LBB18_2
; RV64IM-NEXT: # %bb.1: # %entry
; RV64IM-NEXT: addiw a1, a1, 42
; RV64IM-NEXT: .LBB18_2: # %entry
; RV64IM-NEXT: mv a0, a1
; RV64IM-NEXT: addiw a0, a0, -1
; RV64IM-NEXT: andi a0, a0, 42
; RV64IM-NEXT: addw a0, a1, a0
; RV64IM-NEXT: ret
;
; RV64IMXVTCONDOPS-LABEL: select_add_3:
; RV64IMXVTCONDOPS: # %bb.0: # %entry
; RV64IMXVTCONDOPS-NEXT: addiw a2, a1, 42
; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0
; RV64IMXVTCONDOPS-NEXT: li a2, 42
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0
; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0
; RV64IMXVTCONDOPS-NEXT: addw a0, a1, a0
; RV64IMXVTCONDOPS-NEXT: ret
;
; RV32IMZICOND-LABEL: select_add_3:
Expand All @@ -701,10 +686,9 @@ define i32 @select_add_3(i1 zeroext %cond, i32 %a) {
;
; RV64IMZICOND-LABEL: select_add_3:
; RV64IMZICOND: # %bb.0: # %entry
; RV64IMZICOND-NEXT: addiw a2, a1, 42
; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0
; RV64IMZICOND-NEXT: li a2, 42
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: or a0, a1, a0
; RV64IMZICOND-NEXT: addw a0, a1, a0
; RV64IMZICOND-NEXT: ret
entry:
%c = add i32 %a, 42
Expand Down Expand Up @@ -770,19 +754,15 @@ define i32 @select_sub_2(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV64IM-LABEL: select_sub_2:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: bnez a0, .LBB20_2
; RV64IM-NEXT: # %bb.1: # %entry
; RV64IM-NEXT: subw a1, a1, a2
; RV64IM-NEXT: .LBB20_2: # %entry
; RV64IM-NEXT: mv a0, a1
; RV64IM-NEXT: addiw a0, a0, -1
; RV64IM-NEXT: and a0, a0, a2
; RV64IM-NEXT: subw a0, a1, a0
; RV64IM-NEXT: ret
;
; RV64IMXVTCONDOPS-LABEL: select_sub_2:
; RV64IMXVTCONDOPS: # %bb.0: # %entry
; RV64IMXVTCONDOPS-NEXT: subw a2, a1, a2
; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0
; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0
; RV64IMXVTCONDOPS-NEXT: subw a0, a1, a0
; RV64IMXVTCONDOPS-NEXT: ret
;
; RV32IMZICOND-LABEL: select_sub_2:
Expand All @@ -793,10 +773,8 @@ define i32 @select_sub_2(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV64IMZICOND-LABEL: select_sub_2:
; RV64IMZICOND: # %bb.0: # %entry
; RV64IMZICOND-NEXT: subw a2, a1, a2
; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: or a0, a1, a0
; RV64IMZICOND-NEXT: subw a0, a1, a0
; RV64IMZICOND-NEXT: ret
entry:
%c = sub i32 %a, %b
Expand All @@ -814,19 +792,16 @@ define i32 @select_sub_3(i1 zeroext %cond, i32 %a) {
;
; RV64IM-LABEL: select_sub_3:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: bnez a0, .LBB21_2
; RV64IM-NEXT: # %bb.1: # %entry
; RV64IM-NEXT: addiw a1, a1, -42
; RV64IM-NEXT: .LBB21_2: # %entry
; RV64IM-NEXT: mv a0, a1
; RV64IM-NEXT: addiw a0, a0, -1
; RV64IM-NEXT: andi a0, a0, 42
; RV64IM-NEXT: subw a0, a1, a0
; RV64IM-NEXT: ret
;
; RV64IMXVTCONDOPS-LABEL: select_sub_3:
; RV64IMXVTCONDOPS: # %bb.0: # %entry
; RV64IMXVTCONDOPS-NEXT: addiw a2, a1, -42
; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0
; RV64IMXVTCONDOPS-NEXT: li a2, 42
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0
; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0
; RV64IMXVTCONDOPS-NEXT: subw a0, a1, a0
; RV64IMXVTCONDOPS-NEXT: ret
;
; RV32IMZICOND-LABEL: select_sub_3:
Expand All @@ -838,10 +813,9 @@ define i32 @select_sub_3(i1 zeroext %cond, i32 %a) {
;
; RV64IMZICOND-LABEL: select_sub_3:
; RV64IMZICOND: # %bb.0: # %entry
; RV64IMZICOND-NEXT: addiw a2, a1, -42
; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0
; RV64IMZICOND-NEXT: li a2, 42
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: or a0, a1, a0
; RV64IMZICOND-NEXT: subw a0, a1, a0
; RV64IMZICOND-NEXT: ret
entry:
%c = sub i32 %a, 42
Expand Down
Loading

0 comments on commit 17e2df6

Please sign in to comment.