[AArch64] Update SME load/store intrinsics to work on opaque pointers.

These intrinsics should be able to use opaque pointers, because the load/store type is already encoded in their names and return/operand type. Reviewed By: c-rhodes Differential Revision: https://reviews.llvm.org/D128505
llvm · Jun 28, 2022 · 180cc74 · 180cc74
1 parent f916ee0
commit 180cc74
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Showing 3 changed files with 240 additions and 252 deletions.
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -2586,45 +2586,33 @@ def int_aarch64_sve_whilewr_d : SVE2_CONFLICT_DETECT_Intrinsic;
 
 // Scalable Matrix Extension (SME) Intrinsics
 let TargetPrefix = "aarch64" in {
-  class SME_Load_Store_B_Intrinsic
+  class SME_Load_Store_Intrinsic<LLVMType pred_ty>
     : DefaultAttrsIntrinsic<[],
-        [llvm_nxv16i1_ty, llvm_ptr_ty, llvm_i64_ty, llvm_i32_ty], []>;
-  class SME_Load_Store_H_Intrinsic
-    : DefaultAttrsIntrinsic<[],
-        [llvm_nxv16i1_ty, LLVMPointerType<llvm_i16_ty>, llvm_i64_ty, llvm_i32_ty], []>;
-  class SME_Load_Store_S_Intrinsic
-    : DefaultAttrsIntrinsic<[],
-        [llvm_nxv16i1_ty, LLVMPointerType<llvm_i32_ty>, llvm_i64_ty, llvm_i32_ty], []>;
-  class SME_Load_Store_D_Intrinsic
-    : DefaultAttrsIntrinsic<[],
-        [llvm_nxv16i1_ty, LLVMPointerType<llvm_i64_ty>, llvm_i64_ty, llvm_i32_ty], []>;
-  class SME_Load_Store_Q_Intrinsic
-    : DefaultAttrsIntrinsic<[],
-        [llvm_nxv16i1_ty, LLVMPointerType<llvm_i128_ty>, llvm_i64_ty, llvm_i32_ty], []>;
+        [pred_ty, llvm_ptr_ty, llvm_i64_ty, llvm_i32_ty], []>;
 
   // Loads
-  def int_aarch64_sme_ld1b_horiz : SME_Load_Store_B_Intrinsic;
-  def int_aarch64_sme_ld1h_horiz : SME_Load_Store_H_Intrinsic;
-  def int_aarch64_sme_ld1w_horiz : SME_Load_Store_S_Intrinsic;
-  def int_aarch64_sme_ld1d_horiz : SME_Load_Store_D_Intrinsic;
-  def int_aarch64_sme_ld1q_horiz : SME_Load_Store_Q_Intrinsic;
-  def int_aarch64_sme_ld1b_vert  : SME_Load_Store_B_Intrinsic;
-  def int_aarch64_sme_ld1h_vert  : SME_Load_Store_H_Intrinsic;
-  def int_aarch64_sme_ld1w_vert  : SME_Load_Store_S_Intrinsic;
-  def int_aarch64_sme_ld1d_vert  : SME_Load_Store_D_Intrinsic;
-  def int_aarch64_sme_ld1q_vert  : SME_Load_Store_Q_Intrinsic;
+  def int_aarch64_sme_ld1b_horiz : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_ld1h_horiz : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_ld1w_horiz : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_ld1d_horiz : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_ld1q_horiz : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_ld1b_vert  : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_ld1h_vert  : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_ld1w_vert  : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_ld1d_vert  : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_ld1q_vert  : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
 
   // Stores
-  def int_aarch64_sme_st1b_horiz : SME_Load_Store_B_Intrinsic;
-  def int_aarch64_sme_st1h_horiz : SME_Load_Store_H_Intrinsic;
-  def int_aarch64_sme_st1w_horiz : SME_Load_Store_S_Intrinsic;
-  def int_aarch64_sme_st1d_horiz : SME_Load_Store_D_Intrinsic;
-  def int_aarch64_sme_st1q_horiz : SME_Load_Store_Q_Intrinsic;
-  def int_aarch64_sme_st1b_vert  : SME_Load_Store_B_Intrinsic;
-  def int_aarch64_sme_st1h_vert  : SME_Load_Store_H_Intrinsic;
-  def int_aarch64_sme_st1w_vert  : SME_Load_Store_S_Intrinsic;
-  def int_aarch64_sme_st1d_vert  : SME_Load_Store_D_Intrinsic;
-  def int_aarch64_sme_st1q_vert  : SME_Load_Store_Q_Intrinsic;
+  def int_aarch64_sme_st1b_horiz : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_st1h_horiz : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_st1w_horiz : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_st1d_horiz : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_st1q_horiz : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_st1b_vert  : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_st1h_vert  : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_st1w_vert  : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_st1d_vert  : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
+  def int_aarch64_sme_st1q_vert  : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>;
 
   // Spill + fill
   def int_aarch64_sme_ldr : DefaultAttrsIntrinsic<