[RISCV] Make the min and max vector width command line options more c…

…onsistent and check their relationship to each other.

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

@@ -27,6 +27,12 @@ using namespace llvm;
 #define GET_SUBTARGETINFO_CTOR
 #include "RISCVGenSubtargetInfo.inc"
 
+static cl::opt<unsigned> RVVVectorBitsMax(
+    "riscv-v-vector-bits-max",
+    cl::desc("Assume V extension vector registers are at most this big, "
+             "with zero meaning no maximum size is assumed."),
+    cl::init(0), cl::Hidden);
+
 static cl::opt<unsigned> RVVVectorBitsMin(
     "riscv-v-vector-bits-min",
     cl::desc("Assume V extension vector registers are at least this big, "
@@ -39,11 +45,6 @@ static cl::opt<unsigned> RVVVectorLMULMax(
              "Fractional LMUL values are not supported."),
     cl::init(8), cl::Hidden);
 
-static cl::opt<unsigned> VectorBitsMax(
-    "riscv-vector-bits-max",
-    cl::desc("Assume RISC-V vector registers are at most this big"),
-    cl::init(0), cl::Hidden);
-
 void RISCVSubtarget::anchor() {}
 
 RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
@@ -67,11 +68,6 @@ RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
   return *this;
 }
 
-unsigned RISCVSubtarget::getMaxVectorSizeInBits() const {
-  assert(HasStdExtV && "Tried to get vector length without V support!");
-  return VectorBitsMax;
-}
-
 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
                                StringRef TuneCPU, StringRef FS,
                                StringRef ABIName, const TargetMachine &TM)
@@ -104,14 +100,34 @@ const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
   return RegBankInfo.get();
 }
 
+unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
+  assert(hasStdExtV() && "Tried to get vector length without V support!");
+  if (RVVVectorBitsMax == 0)
+    return 0;
+  assert(RVVVectorBitsMax >= 128 && isPowerOf2_32(RVVVectorBitsMax) &&
+         "V extension requires vector length to be at least 128 and a power of "
+         "2!");
+  assert(RVVVectorBitsMax >= RVVVectorBitsMin &&
+         "Minimum V extension vector length should not be larger than its "
+         "maximum!");
+  unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
+  return PowerOf2Floor(Max < 128 ? 0 : Max);
+}
+
 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
   assert(hasStdExtV() &&
          "Tried to get vector length without V extension support!");
   assert((RVVVectorBitsMin == 0 ||
           (RVVVectorBitsMin >= 128 && isPowerOf2_32(RVVVectorBitsMin))) &&
          "V extension requires vector length to be at least 128 and a power of "
          "2!");
-  return PowerOf2Floor(RVVVectorBitsMin < 128 ? 0 : RVVVectorBitsMin);
+  assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) &&
+         "Minimum V extension vector length should not be larger than its "
+         "maximum!");
+  unsigned Min = RVVVectorBitsMin;
+  if (RVVVectorBitsMax != 0)
+    Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax);
+  return PowerOf2Floor(Min < 128 ? 0 : Min);
 }
 
 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {

llvm/lib/Target/RISCV/RISCVSubtarget.h

@@ -134,7 +134,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
     assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
     return UserReservedRegister[i];
   }
-  unsigned getMaxVectorSizeInBits() const;
 
 protected:
   // GlobalISel related APIs.
@@ -152,6 +151,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   // Return the known range for the bit length of RVV data registers. A value
   // of 0 means nothing is known about that particular limit beyond what's
   // implied by the architecture.
+  unsigned getMaxRVVVectorSizeInBits() const;
   unsigned getMinRVVVectorSizeInBits() const;
   unsigned getLMULForFixedLengthVector(MVT VT) const;
   unsigned getMaxLMULForFixedLengthVectors() const;

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

@@ -129,7 +129,7 @@ Optional<unsigned> RISCVTTIImpl::getMaxVScale() const {
   // If users do not specify the maximum vector length, we have no way to
   // know whether the LoopVectorizer is safe to do or not.
   // We only consider to use single vector register (LMUL = 1) to vectorize.
-  unsigned MaxVectorSizeInBits = ST->getMaxVectorSizeInBits();
+  unsigned MaxVectorSizeInBits = ST->getMaxRVVVectorSizeInBits();
   if (ST->hasStdExtV() && MaxVectorSizeInBits != 0)
     return MaxVectorSizeInBits / RISCV::RVVBitsPerBlock;
   return BaseT::getMaxVScale();

llvm/test/Transforms/LoopVectorize/RISCV/scalable-vf-hint.ll

@@ -1,5 +1,5 @@
 ; RUN: opt -mtriple=riscv64 -mattr=+m,+experimental-v -loop-vectorize \
-; RUN:   -riscv-vector-bits-max=512 -S < %s 2>&1 \
+; RUN:   -riscv-v-vector-bits-max=512 -S < %s 2>&1 \
 ; RUN:   | FileCheck %s
 
 ; void test(int *a, int *b, int N) {