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[RISCV] Always select (and (srl X, C), Mask) as (srli (slli X, C2), C3).
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SLLI is always compressible to C.SLLI as long as the source and dest
register is the same.

ANDI and SRLI are only compressible if the register is x8-x15. By
using SLLI we have a better chance of generating shorter code.

I had to exclude one exclusion for the BEXTI case so that it's
pattern match could still fire.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D123336
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@topperc
topperc committed Apr 8, 2022
1 parent 57f4dcf commit 1903b99
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Showing 9 changed files with 88 additions and 86 deletions.
6 changes: 4 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
View file
Expand Up @@ -776,11 +776,13 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
}

// (srli (slli x, c3-c2), c3).
// Skip it in order to select sraiw.
// Skip if we could use (zext.w (sraiw X, C2)).
bool Skip = Subtarget->hasStdExtZba() && C3 == 32 &&
X.getOpcode() == ISD::SIGN_EXTEND_INREG &&
cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32;
if (OneUseOrZExtW && !IsCANDI && !Skip) {
// Also Skip if we can use bexti.
Skip |= Subtarget->hasStdExtZbs() && C3 == XLen - 1;
if (OneUseOrZExtW && !Skip) {
SDNode *SLLI = CurDAG->getMachineNode(
RISCV::SLLI, DL, XLenVT, X,
CurDAG->getTargetConstant(C3 - C2, DL, XLenVT));
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/RISCV/div-by-constant.ll
View file
Expand Up @@ -526,8 +526,8 @@ define i8 @sdiv8_constant_no_srai(i8 %a) nounwind {
; RV32IM-NEXT: li a1, 86
; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: srli a1, a0, 8
; RV32IM-NEXT: srli a0, a0, 15
; RV32IM-NEXT: andi a0, a0, 1
; RV32IM-NEXT: slli a0, a0, 16
; RV32IM-NEXT: srli a0, a0, 31
; RV32IM-NEXT: add a0, a1, a0
; RV32IM-NEXT: ret
;
Expand All @@ -537,8 +537,8 @@ define i8 @sdiv8_constant_no_srai(i8 %a) nounwind {
; RV32IMZB-NEXT: li a1, 86
; RV32IMZB-NEXT: mul a0, a0, a1
; RV32IMZB-NEXT: srli a1, a0, 8
; RV32IMZB-NEXT: srli a0, a0, 15
; RV32IMZB-NEXT: andi a0, a0, 1
; RV32IMZB-NEXT: slli a0, a0, 16
; RV32IMZB-NEXT: srli a0, a0, 31
; RV32IMZB-NEXT: add a0, a1, a0
; RV32IMZB-NEXT: ret
;
Expand All @@ -549,8 +549,8 @@ define i8 @sdiv8_constant_no_srai(i8 %a) nounwind {
; RV64IM-NEXT: li a1, 86
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a1, a0, 8
; RV64IM-NEXT: srli a0, a0, 15
; RV64IM-NEXT: andi a0, a0, 1
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: srli a0, a0, 63
; RV64IM-NEXT: add a0, a1, a0
; RV64IM-NEXT: ret
;
Expand All @@ -560,8 +560,8 @@ define i8 @sdiv8_constant_no_srai(i8 %a) nounwind {
; RV64IMZB-NEXT: li a1, 86
; RV64IMZB-NEXT: mul a0, a0, a1
; RV64IMZB-NEXT: srli a1, a0, 8
; RV64IMZB-NEXT: srli a0, a0, 15
; RV64IMZB-NEXT: andi a0, a0, 1
; RV64IMZB-NEXT: slli a0, a0, 48
; RV64IMZB-NEXT: srli a0, a0, 63
; RV64IMZB-NEXT: add a0, a1, a0
; RV64IMZB-NEXT: ret
%1 = sdiv i8 %a, 3
Expand All @@ -576,8 +576,8 @@ define i8 @sdiv8_constant_srai(i8 %a) nounwind {
; RV32IM-NEXT: li a1, 103
; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: srai a1, a0, 9
; RV32IM-NEXT: srli a0, a0, 15
; RV32IM-NEXT: andi a0, a0, 1
; RV32IM-NEXT: slli a0, a0, 16
; RV32IM-NEXT: srli a0, a0, 31
; RV32IM-NEXT: add a0, a1, a0
; RV32IM-NEXT: ret
;
Expand All @@ -587,8 +587,8 @@ define i8 @sdiv8_constant_srai(i8 %a) nounwind {
; RV32IMZB-NEXT: li a1, 103
; RV32IMZB-NEXT: mul a0, a0, a1
; RV32IMZB-NEXT: srai a1, a0, 9
; RV32IMZB-NEXT: srli a0, a0, 15
; RV32IMZB-NEXT: andi a0, a0, 1
; RV32IMZB-NEXT: slli a0, a0, 16
; RV32IMZB-NEXT: srli a0, a0, 31
; RV32IMZB-NEXT: add a0, a1, a0
; RV32IMZB-NEXT: ret
;
Expand All @@ -599,8 +599,8 @@ define i8 @sdiv8_constant_srai(i8 %a) nounwind {
; RV64IM-NEXT: li a1, 103
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srai a1, a0, 9
; RV64IM-NEXT: srli a0, a0, 15
; RV64IM-NEXT: andi a0, a0, 1
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: srli a0, a0, 63
; RV64IM-NEXT: add a0, a1, a0
; RV64IM-NEXT: ret
;
Expand All @@ -610,8 +610,8 @@ define i8 @sdiv8_constant_srai(i8 %a) nounwind {
; RV64IMZB-NEXT: li a1, 103
; RV64IMZB-NEXT: mul a0, a0, a1
; RV64IMZB-NEXT: srai a1, a0, 9
; RV64IMZB-NEXT: srli a0, a0, 15
; RV64IMZB-NEXT: andi a0, a0, 1
; RV64IMZB-NEXT: slli a0, a0, 48
; RV64IMZB-NEXT: srli a0, a0, 63
; RV64IMZB-NEXT: add a0, a1, a0
; RV64IMZB-NEXT: ret
%1 = sdiv i8 %a, 5
Expand Down
40 changes: 20 additions & 20 deletions llvm/test/CodeGen/RISCV/div.ll
View file
Expand Up @@ -1031,8 +1031,8 @@ define i8 @sdiv8_constant(i8 %a) nounwind {
; RV32IM-NEXT: li a1, 103
; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: srai a1, a0, 9
; RV32IM-NEXT: srli a0, a0, 15
; RV32IM-NEXT: andi a0, a0, 1
; RV32IM-NEXT: slli a0, a0, 16
; RV32IM-NEXT: srli a0, a0, 31
; RV32IM-NEXT: add a0, a1, a0
; RV32IM-NEXT: ret
;
Expand All @@ -1055,8 +1055,8 @@ define i8 @sdiv8_constant(i8 %a) nounwind {
; RV64IM-NEXT: li a1, 103
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srai a1, a0, 9
; RV64IM-NEXT: srli a0, a0, 15
; RV64IM-NEXT: andi a0, a0, 1
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: srli a0, a0, 63
; RV64IM-NEXT: add a0, a1, a0
; RV64IM-NEXT: ret
%1 = sdiv i8 %a, 5
Expand All @@ -1068,8 +1068,8 @@ define i8 @sdiv8_pow2(i8 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 24
; RV32I-NEXT: srai a1, a1, 24
; RV32I-NEXT: srli a1, a1, 12
; RV32I-NEXT: andi a1, a1, 7
; RV32I-NEXT: slli a1, a1, 17
; RV32I-NEXT: srli a1, a1, 29
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 27
Expand All @@ -1079,8 +1079,8 @@ define i8 @sdiv8_pow2(i8 %a) nounwind {
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a1, a0, 24
; RV32IM-NEXT: srai a1, a1, 24
; RV32IM-NEXT: srli a1, a1, 12
; RV32IM-NEXT: andi a1, a1, 7
; RV32IM-NEXT: slli a1, a1, 17
; RV32IM-NEXT: srli a1, a1, 29
; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: slli a0, a0, 24
; RV32IM-NEXT: srai a0, a0, 27
Expand All @@ -1090,8 +1090,8 @@ define i8 @sdiv8_pow2(i8 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 56
; RV64I-NEXT: srai a1, a1, 56
; RV64I-NEXT: srli a1, a1, 12
; RV64I-NEXT: andi a1, a1, 7
; RV64I-NEXT: slli a1, a1, 49
; RV64I-NEXT: srli a1, a1, 61
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 59
Expand All @@ -1101,8 +1101,8 @@ define i8 @sdiv8_pow2(i8 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 56
; RV64IM-NEXT: srai a1, a1, 56
; RV64IM-NEXT: srli a1, a1, 12
; RV64IM-NEXT: andi a1, a1, 7
; RV64IM-NEXT: slli a1, a1, 49
; RV64IM-NEXT: srli a1, a1, 61
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 56
; RV64IM-NEXT: srai a0, a0, 59
Expand Down Expand Up @@ -1260,8 +1260,8 @@ define i16 @sdiv16_pow2(i16 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 16
; RV32I-NEXT: srai a1, a1, 16
; RV32I-NEXT: srli a1, a1, 28
; RV32I-NEXT: andi a1, a1, 7
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: srli a1, a1, 29
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srai a0, a0, 19
Expand All @@ -1271,8 +1271,8 @@ define i16 @sdiv16_pow2(i16 %a) nounwind {
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a1, a0, 16
; RV32IM-NEXT: srai a1, a1, 16
; RV32IM-NEXT: srli a1, a1, 28
; RV32IM-NEXT: andi a1, a1, 7
; RV32IM-NEXT: slli a1, a1, 1
; RV32IM-NEXT: srli a1, a1, 29
; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: slli a0, a0, 16
; RV32IM-NEXT: srai a0, a0, 19
Expand All @@ -1282,8 +1282,8 @@ define i16 @sdiv16_pow2(i16 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 48
; RV64I-NEXT: srai a1, a1, 48
; RV64I-NEXT: srli a1, a1, 28
; RV64I-NEXT: andi a1, a1, 7
; RV64I-NEXT: slli a1, a1, 33
; RV64I-NEXT: srli a1, a1, 61
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 51
Expand All @@ -1293,8 +1293,8 @@ define i16 @sdiv16_pow2(i16 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 48
; RV64IM-NEXT: srai a1, a1, 48
; RV64IM-NEXT: srli a1, a1, 28
; RV64IM-NEXT: andi a1, a1, 7
; RV64IM-NEXT: slli a1, a1, 33
; RV64IM-NEXT: srli a1, a1, 61
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: srai a0, a0, 51
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rv32zbb-zbp-zbkb.ll
View file
Expand Up @@ -140,8 +140,8 @@ declare i64 @llvm.fshl.i64(i64, i64, i64)
define i64 @rol_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: rol_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a3, a2, 5
; RV32I-NEXT: andi a3, a3, 1
; RV32I-NEXT: slli a3, a2, 26
; RV32I-NEXT: srli a3, a3, 31
; RV32I-NEXT: mv a4, a1
; RV32I-NEXT: bnez a3, .LBB7_2
; RV32I-NEXT: # %bb.1:
Expand All @@ -165,8 +165,8 @@ define i64 @rol_i64(i64 %a, i64 %b) nounwind {
;
; RV32ZBB-ZBP-ZBKB-LABEL: rol_i64:
; RV32ZBB-ZBP-ZBKB: # %bb.0:
; RV32ZBB-ZBP-ZBKB-NEXT: srli a3, a2, 5
; RV32ZBB-ZBP-ZBKB-NEXT: andi a3, a3, 1
; RV32ZBB-ZBP-ZBKB-NEXT: slli a3, a2, 26
; RV32ZBB-ZBP-ZBKB-NEXT: srli a3, a3, 31
; RV32ZBB-ZBP-ZBKB-NEXT: mv a4, a1
; RV32ZBB-ZBP-ZBKB-NEXT: bnez a3, .LBB7_2
; RV32ZBB-ZBP-ZBKB-NEXT: # %bb.1:
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rv32zbs.ll
View file
Expand Up @@ -324,8 +324,8 @@ define i64 @bext_i64(i64 %a, i64 %b) nounwind {
define i32 @bexti_i32(i32 %a) nounwind {
; RV32I-LABEL: bexti_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 5
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: slli a0, a0, 26
; RV32I-NEXT: srli a0, a0, 31
; RV32I-NEXT: ret
;
; RV32ZBS-LABEL: bexti_i32:
Expand All @@ -340,8 +340,8 @@ define i32 @bexti_i32(i32 %a) nounwind {
define i64 @bexti_i64(i64 %a) nounwind {
; RV32I-LABEL: bexti_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 5
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: slli a0, a0, 26
; RV32I-NEXT: srli a0, a0, 31
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
;
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rv32zbt.ll
View file
Expand Up @@ -799,8 +799,8 @@ declare i64 @llvm.fshl.i64(i64, i64, i64)
define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: fshl_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a5, a4, 5
; RV32I-NEXT: andi a6, a5, 1
; RV32I-NEXT: slli a5, a4, 26
; RV32I-NEXT: srli a6, a5, 31
; RV32I-NEXT: mv a5, a3
; RV32I-NEXT: bnez a6, .LBB36_2
; RV32I-NEXT: # %bb.1:
Expand Down Expand Up @@ -828,8 +828,8 @@ define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
;
; RV32ZBT-LABEL: fshl_i64:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: srli a5, a4, 5
; RV32ZBT-NEXT: andi a5, a5, 1
; RV32ZBT-NEXT: slli a5, a4, 26
; RV32ZBT-NEXT: srli a5, a5, 31
; RV32ZBT-NEXT: cmov a2, a5, a2, a3
; RV32ZBT-NEXT: cmov a3, a5, a3, a0
; RV32ZBT-NEXT: andi a4, a4, 31
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rv64zbs.ll
View file
Expand Up @@ -409,8 +409,8 @@ define i64 @bext_i64_no_mask(i64 %a, i64 %b) nounwind {
define signext i32 @bexti_i32(i32 signext %a) nounwind {
; RV64I-LABEL: bexti_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 5
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: slli a0, a0, 58
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bexti_i32:
Expand All @@ -425,8 +425,8 @@ define signext i32 @bexti_i32(i32 signext %a) nounwind {
define i64 @bexti_i64(i64 %a) nounwind {
; RV64I-LABEL: bexti_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 5
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: slli a0, a0, 58
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bexti_i64:
Expand Down

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